diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-07 10:17:56 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-07 10:17:56 +0200 |
| commit | f1615bbe9be4def59c3b3eaddb60722efeed16c2 (patch) | |
| tree | ca3020e65447576fc1826e819651e6ba072030b5 /drivers/video/fbdev/mmp/hw/mmp_ctrl.h | |
| parent | cfb3c0ab0903abb6ea5215b37eebd9c2a1f057eb (diff) | |
| parent | cd3de83f147601356395b57a8673e9c5ff1e59d1 (diff) | |
Merge tag 'v3.16-rc4' into drm-intel-next-queued
Due to Dave's vacation drm-next hasn't opened yet for 3.17 so I
couldn't move my drm-intel-next queue forward yet like I usually do.
Just pull in the latest upstream -rc to unblock patch merging - I
don't want to needlessly rebase my current patch pile really and void
all the testing we've done already.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/video/fbdev/mmp/hw/mmp_ctrl.h')
| -rw-r--r-- | drivers/video/fbdev/mmp/hw/mmp_ctrl.h | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/drivers/video/fbdev/mmp/hw/mmp_ctrl.h b/drivers/video/fbdev/mmp/hw/mmp_ctrl.h index 53301cfdb1a..56fdeab3435 100644 --- a/drivers/video/fbdev/mmp/hw/mmp_ctrl.h +++ b/drivers/video/fbdev/mmp/hw/mmp_ctrl.h @@ -167,11 +167,7 @@ struct lcd_regs { PN2_IOPAD_CONTROL) : LCD_TOP_CTRL) /* dither configure */ -#ifdef CONFIG_CPU_PXA988 -#define LCD_DITHER_CTRL (0x01EC) -#else #define LCD_DITHER_CTRL (0x00A0) -#endif #define DITHER_TBL_INDEX_SEL(s) ((s) << 16) #define DITHER_MODE2(m) ((m) << 12) @@ -186,15 +182,6 @@ struct lcd_regs { #define DITHER_EN1 (1) /* dither table data was fixed by video bpp of input and output*/ -#ifdef CONFIG_CPU_PXA988 -#define DITHER_TB_4X4_INDEX0 (0x6e4ca280) -#define DITHER_TB_4X4_INDEX1 (0x5d7f91b3) -#define DITHER_TB_4X8_INDEX0 (0xb391a280) -#define DITHER_TB_4X8_INDEX1 (0x7f5d6e4c) -#define DITHER_TB_4X8_INDEX2 (0x80a291b3) -#define DITHER_TB_4X8_INDEX3 (0x4c6e5d7f) -#define LCD_DITHER_TBL_DATA (0x01F0) -#else #define DITHER_TB_4X4_INDEX0 (0x3b19f7d5) #define DITHER_TB_4X4_INDEX1 (0x082ac4e6) #define DITHER_TB_4X8_INDEX0 (0xf7d508e6) @@ -202,7 +189,6 @@ struct lcd_regs { #define DITHER_TB_4X8_INDEX2 (0xc4e6d5f7) #define DITHER_TB_4X8_INDEX3 (0x082a193b) #define LCD_DITHER_TBL_DATA (0x00A4) -#endif /* Video Frame 0&1 start address registers */ #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0 @@ -933,16 +919,9 @@ struct lcd_regs { #define LCD_PN2_SQULN2_CTRL (0x02F0) #define ALL_LAYER_ALPHA_SEL (0x02F4) -/* pxa988 has different MASTER_CTRL from MMP3/MMP2 */ -#ifdef CONFIG_CPU_PXA988 -#define TIMING_MASTER_CONTROL (0x01F4) -#define MASTER_ENH(id) (1 << ((id) + 5)) -#define MASTER_ENV(id) (1 << ((id) + 6)) -#else #define TIMING_MASTER_CONTROL (0x02F8) #define MASTER_ENH(id) (1 << (id)) #define MASTER_ENV(id) (1 << ((id) + 4)) -#endif #define DSI_START_SEL_SHIFT(id) (((id) << 1) + 8) #define timing_master_config(path, dsi_id, lcd_id) \ @@ -1312,19 +1291,8 @@ struct dsi_regs { #define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_MASK (0xff) #define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_SHIFT 0 -/* - * DSI timings - * PXA988 has diffrent ESC CLK with MMP2/MMP3 - * it will be used in dsi_set_dphy() in pxa688_phy.c - * as low power mode clock. - */ -#ifdef CONFIG_CPU_PXA988 -#define DSI_ESC_CLK 52 /* Unit: Mhz */ -#define DSI_ESC_CLK_T 19 /* Unit: ns */ -#else #define DSI_ESC_CLK 66 /* Unit: Mhz */ #define DSI_ESC_CLK_T 15 /* Unit: ns */ -#endif /* LVDS */ /* LVDS_PHY_CTRL */ |