diff options
| author | Nicolas Dufresne <nicolas.dufresne@collabora.com> | 2014-12-15 18:10:57 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@osg.samsung.com> | 2015-02-02 09:57:14 -0200 |
| commit | 1b880ef62cc43d049bd92a31a0612caacb5f30b2 (patch) | |
| tree | 4d563e0add87f65fd6561b2a48312a7a90dc175e /drivers | |
| parent | a5f43c18fceb2b96ec9fddb4348f5282a71cf2b0 (diff) | |
[media] s5p-mfc-v6+: Use display_delay_enable CID
The MFC driver has two controls, DISPLAY_DELAY and DISPLAY_DELAY_ENABLE
that allow forcing the decoder to return a decoded frame sooner
regardless of the order. The added support for firmware version 6 and
higher was not taking into account the DISPLAY_DELAY_ENABLE boolean.
Instead it had a comment stating that DISPLAY_DELAY should be set to a
negative value to disable it. This is not possible since the control
range is from 0 to 65535. This feature was also supposed to be disabled
by default in order to produce frames in display order.
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Acked-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c index 9aea179943c..d826c58b5d5 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c @@ -1340,11 +1340,7 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx) /* FMO_ASO_CTRL - 0: Enable, 1: Disable */ reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6); - /* When user sets desplay_delay to 0, - * It works as "display_delay enable" and delay set to 0. - * If user wants display_delay disable, It should be - * set to negative value. */ - if (ctx->display_delay >= 0) { + if (ctx->display_delay_enable) { reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6); writel(ctx->display_delay, mfc_regs->d_display_delay); } |