diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2006-09-14 13:29:15 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-09-14 13:29:15 +0100 |
| commit | c84cbb246e5a5235af30ddbe49d23bb1eaf64add (patch) | |
| tree | 90ba1f16e562a64d4efe6e23470a90c74f9006e5 /include/asm-arm/arch-s3c2410/regs-power.h | |
| parent | a55ee0ea51ae8f622cb3d69d81a47cb772952f73 (diff) | |
[ARM] 3785/1: S3C2412: Fix idle code as default uses wrong clocks
Patch from Ben Dooks
Fix the idle code on the s3c2412 as the default
code is using bits in the CLKCON register that are
no-longer there.
Provide an override for the idle code, and ensure
that the power configuration is set to allow idle
instead of stop or sleep.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-power.h')
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-power.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-power.h b/include/asm-arm/arch-s3c2410/regs-power.h new file mode 100644 index 00000000000..6c319ea2afa --- /dev/null +++ b/include/asm-arm/arch-s3c2410/regs-power.h @@ -0,0 +1,34 @@ +/* linux/include/asm/arch-s3c2410/regs-power.h + * + * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C24XX power control register definitions +*/ + +#ifndef __ASM_ARM_REGS_PWR +#define __ASM_ARM_REGS_PWR __FILE__ + +#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR) + +#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) +#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) + +#define S3C2412_PWRCFG_BATF_IGNORE (0<<0) +#define S3C2412_PWRCFG_BATF_SLEEP (3<<0) +#define S3C2412_PWRCFG_BATF_MASK (3<<0) + +#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6) +#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6) +#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6) +#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6) +#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6) + +#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8) +#define S3C2412_PWRCFG_NAND_NORST (1<<9) + +#endif /* __ASM_ARM_REGS_PWR */ |