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author | Ben Dooks <ben-linux@fluff.org> | 2008-07-15 20:19:14 +0100 |
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committer | Ben Dooks <ben-linux@fluff.org> | 2008-07-15 20:19:14 +0100 |
commit | 0c17e4ceedd35c78b1c7413dbd16279a350be6bc (patch) | |
tree | 313b3b9ca04727f3704464e01d8dd97da1dd534b /include/asm-arm/assembler.h | |
parent | 19c1d6a34abf73d0baf8e325d018c920fa78dddc (diff) | |
parent | b9d2252c1e44fa83a4e65fdc9eb93db6297c55af (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into for-rmk
Diffstat (limited to 'include/asm-arm/assembler.h')
-rw-r--r-- | include/asm-arm/assembler.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h index fce83282082..911393b2c6f 100644 --- a/include/asm-arm/assembler.h +++ b/include/asm-arm/assembler.h @@ -56,6 +56,21 @@ #endif /* + * This can be used to enable code to cacheline align the destination + * pointer when bulk writing to memory. Experiments on StrongARM and + * XScale didn't show this a worthwhile thing to do when the cache is not + * set to write-allocate (this would need further testing on XScale when WA + * is used). + * + * On Feroceon there is much to gain however, regardless of cache mode. + */ +#ifdef CONFIG_CPU_FEROCEON +#define CALGN(code...) code +#else +#define CALGN(code...) +#endif + +/* * Enable and disable interrupts */ #if __LINUX_ARM_ARCH__ >= 6 |