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| author | Ingo Molnar <mingo@elte.hu> | 2008-07-30 19:36:55 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-30 19:36:55 +0200 |
| commit | bc588df79ebfb710abc27342fccf336a68ed1216 (patch) | |
| tree | e50e125eaa6da83fa715704e53c1bde013d1ef8e /include/asm-arm/assembler.h | |
| parent | bce7f793daec3e65ec5c5705d2457b81fe7b5725 (diff) | |
| parent | 15dd859cacf312f606f54502d1f66537a1e5c78c (diff) | |
Merge branch 'x86/core' into x86/xsave
Diffstat (limited to 'include/asm-arm/assembler.h')
| -rw-r--r-- | include/asm-arm/assembler.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h index fce83282082..911393b2c6f 100644 --- a/include/asm-arm/assembler.h +++ b/include/asm-arm/assembler.h @@ -56,6 +56,21 @@ #endif /* + * This can be used to enable code to cacheline align the destination + * pointer when bulk writing to memory. Experiments on StrongARM and + * XScale didn't show this a worthwhile thing to do when the cache is not + * set to write-allocate (this would need further testing on XScale when WA + * is used). + * + * On Feroceon there is much to gain however, regardless of cache mode. + */ +#ifdef CONFIG_CPU_FEROCEON +#define CALGN(code...) code +#else +#define CALGN(code...) +#endif + +/* * Enable and disable interrupts */ #if __LINUX_ARM_ARCH__ >= 6 |