MIPS: Move headfiles to new location below arch/mips/include

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

13 files changed, 0 insertions, 3786 deletions

diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
deleted file mode 100644
index 0d302bad449..00000000000
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ /dev/null
@@ -1,1772 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *	Include file for Alchemy Semiconductor's Au1k CPU.
- *
- * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
- /*
-  * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
-  */
-
-#ifndef _AU1000_H_
-#define _AU1000_H_
-
-
-#ifndef _LANGUAGE_ASSEMBLY
-
-#include <linux/delay.h>
-#include <linux/types.h>
-
-#include <linux/io.h>
-#include <linux/irq.h>
-
-/* cpu pipeline flush */
-void static inline au_sync(void)
-{
-	__asm__ volatile ("sync");
-}
-
-void static inline au_sync_udelay(int us)
-{
-	__asm__ volatile ("sync");
-	udelay(us);
-}
-
-void static inline au_sync_delay(int ms)
-{
-	__asm__ volatile ("sync");
-	mdelay(ms);
-}
-
-void static inline au_writeb(u8 val, unsigned long reg)
-{
-	*(volatile u8 *)reg = val;
-}
-
-void static inline au_writew(u16 val, unsigned long reg)
-{
-	*(volatile u16 *)reg = val;
-}
-
-void static inline au_writel(u32 val, unsigned long reg)
-{
-	*(volatile u32 *)reg = val;
-}
-
-static inline u8 au_readb(unsigned long reg)
-{
-	return *(volatile u8 *)reg;
-}
-
-static inline u16 au_readw(unsigned long reg)
-{
-	return *(volatile u16 *)reg;
-}
-
-static inline u32 au_readl(unsigned long reg)
-{
-	return *(volatile u32 *)reg;
-}
-
-
-/* arch/mips/au1000/common/clocks.c */
-extern void set_au1x00_speed(unsigned int new_freq);
-extern unsigned int get_au1x00_speed(void);
-extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
-extern unsigned long get_au1x00_uart_baud_base(void);
-extern void set_au1x00_lcd_clock(void);
-extern unsigned int get_au1x00_lcd_clock(void);
-
-/*
- * Every board describes its IRQ mapping with this table.
- */
-struct au1xxx_irqmap {
-	int	im_irq;
-	int	im_type;
-	int	im_request;
-};
-
-/*
- * init_IRQ looks for a table with this name.
- */
-extern struct au1xxx_irqmap au1xxx_irq_map[];
-
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
-
-/*
- * SDRAM register offsets
- */
-#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
-    defined(CONFIG_SOC_AU1100)
-#define MEM_SDMODE0		0x0000
-#define MEM_SDMODE1		0x0004
-#define MEM_SDMODE2		0x0008
-#define MEM_SDADDR0		0x000C
-#define MEM_SDADDR1		0x0010
-#define MEM_SDADDR2		0x0014
-#define MEM_SDREFCFG		0x0018
-#define MEM_SDPRECMD		0x001C
-#define MEM_SDAUTOREF		0x0020
-#define MEM_SDWRMD0		0x0024
-#define MEM_SDWRMD1		0x0028
-#define MEM_SDWRMD2		0x002C
-#define MEM_SDSLEEP		0x0030
-#define MEM_SDSMCKE		0x0034
-
-/*
- * MEM_SDMODE register content definitions
- */
-#define MEM_SDMODE_F		(1 << 22)
-#define MEM_SDMODE_SR		(1 << 21)
-#define MEM_SDMODE_BS		(1 << 20)
-#define MEM_SDMODE_RS		(3 << 18)
-#define MEM_SDMODE_CS		(7 << 15)
-#define MEM_SDMODE_TRAS 	(15 << 11)
-#define MEM_SDMODE_TMRD 	(3 << 9)
-#define MEM_SDMODE_TWR		(3 << 7)
-#define MEM_SDMODE_TRP		(3 << 5)
-#define MEM_SDMODE_TRCD 	(3 << 3)
-#define MEM_SDMODE_TCL		(7 << 0)
-
-#define MEM_SDMODE_BS_2Bank	(0 << 20)
-#define MEM_SDMODE_BS_4Bank	(1 << 20)
-#define MEM_SDMODE_RS_11Row	(0 << 18)
-#define MEM_SDMODE_RS_12Row	(1 << 18)
-#define MEM_SDMODE_RS_13Row	(2 << 18)
-#define MEM_SDMODE_RS_N(N)	((N) << 18)
-#define MEM_SDMODE_CS_7Col	(0 << 15)
-#define MEM_SDMODE_CS_8Col	(1 << 15)
-#define MEM_SDMODE_CS_9Col	(2 << 15)
-#define MEM_SDMODE_CS_10Col	(3 << 15)
-#define MEM_SDMODE_CS_11Col	(4 << 15)
-#define MEM_SDMODE_CS_N(N)	((N) << 15)
-#define MEM_SDMODE_TRAS_N(N)	((N) << 11)
-#define MEM_SDMODE_TMRD_N(N)	((N) << 9)
-#define MEM_SDMODE_TWR_N(N)	((N) << 7)
-#define MEM_SDMODE_TRP_N(N)	((N) << 5)
-#define MEM_SDMODE_TRCD_N(N)	((N) << 3)
-#define MEM_SDMODE_TCL_N(N)	((N) << 0)
-
-/*
- * MEM_SDADDR register contents definitions
- */
-#define MEM_SDADDR_E		(1 << 20)
-#define MEM_SDADDR_CSBA 	(0x03FF << 10)
-#define MEM_SDADDR_CSMASK	(0x03FF << 0)
-#define MEM_SDADDR_CSBA_N(N)	((N) & (0x03FF << 22) >> 12)
-#define MEM_SDADDR_CSMASK_N(N)	((N)&(0x03FF << 22) >> 22)
-
-/*
- * MEM_SDREFCFG register content definitions
- */
-#define MEM_SDREFCFG_TRC	(15 << 28)
-#define MEM_SDREFCFG_TRPM	(3 << 26)
-#define MEM_SDREFCFG_E		(1 << 25)
-#define MEM_SDREFCFG_RE 	(0x1ffffff << 0)
-#define MEM_SDREFCFG_TRC_N(N)	((N) << MEM_SDREFCFG_TRC)
-#define MEM_SDREFCFG_TRPM_N(N)	((N) << MEM_SDREFCFG_TRPM)
-#define MEM_SDREFCFG_REF_N(N)	(N)
-#endif
-
-/***********************************************************************/
-
-/*
- * Au1550 SDRAM Register Offsets
- */
-
-/***********************************************************************/
-
-#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-#define MEM_SDMODE0		0x0800
-#define MEM_SDMODE1		0x0808
-#define MEM_SDMODE2		0x0810
-#define MEM_SDADDR0		0x0820
-#define MEM_SDADDR1		0x0828
-#define MEM_SDADDR2		0x0830
-#define MEM_SDCONFIGA		0x0840
-#define MEM_SDCONFIGB		0x0848
-#define MEM_SDSTAT		0x0850
-#define MEM_SDERRADDR		0x0858
-#define MEM_SDSTRIDE0		0x0860
-#define MEM_SDSTRIDE1		0x0868
-#define MEM_SDSTRIDE2		0x0870
-#define MEM_SDWRMD0		0x0880
-#define MEM_SDWRMD1		0x0888
-#define MEM_SDWRMD2		0x0890
-#define MEM_SDPRECMD		0x08C0
-#define MEM_SDAUTOREF		0x08C8
-#define MEM_SDSREF		0x08D0
-#define MEM_SDSLEEP		MEM_SDSREF
-
-#endif
-
-/*
- * Physical base addresses for integrated peripherals
- */
-
-#ifdef CONFIG_SOC_AU1000
-#define	MEM_PHYS_ADDR		0x14000000
-#define	STATIC_MEM_PHYS_ADDR	0x14001000
-#define	DMA0_PHYS_ADDR		0x14002000
-#define	DMA1_PHYS_ADDR		0x14002100
-#define	DMA2_PHYS_ADDR		0x14002200
-#define	DMA3_PHYS_ADDR		0x14002300
-#define	DMA4_PHYS_ADDR		0x14002400
-#define	DMA5_PHYS_ADDR		0x14002500
-#define	DMA6_PHYS_ADDR		0x14002600
-#define	DMA7_PHYS_ADDR		0x14002700
-#define	IC0_PHYS_ADDR		0x10400000
-#define	IC1_PHYS_ADDR		0x11800000
-#define	AC97_PHYS_ADDR		0x10000000
-#define	USBH_PHYS_ADDR		0x10100000
-#define	USBD_PHYS_ADDR		0x10200000
-#define	IRDA_PHYS_ADDR		0x10300000
-#define	MAC0_PHYS_ADDR		0x10500000
-#define	MAC1_PHYS_ADDR		0x10510000
-#define	MACEN_PHYS_ADDR		0x10520000
-#define	MACDMA0_PHYS_ADDR	0x14004000
-#define	MACDMA1_PHYS_ADDR	0x14004200
-#define	I2S_PHYS_ADDR		0x11000000
-#define	UART0_PHYS_ADDR		0x11100000
-#define	UART1_PHYS_ADDR		0x11200000
-#define	UART2_PHYS_ADDR		0x11300000
-#define	UART3_PHYS_ADDR		0x11400000
-#define	SSI0_PHYS_ADDR		0x11600000
-#define	SSI1_PHYS_ADDR		0x11680000
-#define	SYS_PHYS_ADDR		0x11900000
-#define PCMCIA_IO_PHYS_ADDR	0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR	0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR	0xF80000000ULL
-#endif
-
-/********************************************************************/
-
-#ifdef CONFIG_SOC_AU1500
-#define	MEM_PHYS_ADDR		0x14000000
-#define	STATIC_MEM_PHYS_ADDR	0x14001000
-#define	DMA0_PHYS_ADDR		0x14002000
-#define	DMA1_PHYS_ADDR		0x14002100
-#define	DMA2_PHYS_ADDR		0x14002200
-#define	DMA3_PHYS_ADDR		0x14002300
-#define	DMA4_PHYS_ADDR		0x14002400
-#define	DMA5_PHYS_ADDR		0x14002500
-#define	DMA6_PHYS_ADDR		0x14002600
-#define	DMA7_PHYS_ADDR		0x14002700
-#define	IC0_PHYS_ADDR		0x10400000
-#define	IC1_PHYS_ADDR		0x11800000
-#define	AC97_PHYS_ADDR		0x10000000
-#define	USBH_PHYS_ADDR		0x10100000
-#define	USBD_PHYS_ADDR		0x10200000
-#define PCI_PHYS_ADDR		0x14005000
-#define	MAC0_PHYS_ADDR		0x11500000
-#define	MAC1_PHYS_ADDR		0x11510000
-#define	MACEN_PHYS_ADDR		0x11520000
-#define	MACDMA0_PHYS_ADDR	0x14004000
-#define	MACDMA1_PHYS_ADDR	0x14004200
-#define	I2S_PHYS_ADDR		0x11000000
-#define	UART0_PHYS_ADDR		0x11100000
-#define	UART3_PHYS_ADDR		0x11400000
-#define GPIO2_PHYS_ADDR		0x11700000
-#define	SYS_PHYS_ADDR		0x11900000
-#define PCI_MEM_PHYS_ADDR	0x400000000ULL
-#define PCI_IO_PHYS_ADDR	0x500000000ULL
-#define PCI_CONFIG0_PHYS_ADDR	0x600000000ULL
-#define PCI_CONFIG1_PHYS_ADDR	0x680000000ULL
-#define PCMCIA_IO_PHYS_ADDR	0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR	0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR	0xF80000000ULL
-#endif
-
-/********************************************************************/
-
-#ifdef CONFIG_SOC_AU1100
-#define	MEM_PHYS_ADDR		0x14000000
-#define	STATIC_MEM_PHYS_ADDR	0x14001000
-#define	DMA0_PHYS_ADDR		0x14002000
-#define	DMA1_PHYS_ADDR		0x14002100
-#define	DMA2_PHYS_ADDR		0x14002200
-#define	DMA3_PHYS_ADDR		0x14002300
-#define	DMA4_PHYS_ADDR		0x14002400
-#define	DMA5_PHYS_ADDR		0x14002500
-#define	DMA6_PHYS_ADDR		0x14002600
-#define	DMA7_PHYS_ADDR		0x14002700
-#define	IC0_PHYS_ADDR		0x10400000
-#define SD0_PHYS_ADDR		0x10600000
-#define SD1_PHYS_ADDR		0x10680000
-#define	IC1_PHYS_ADDR		0x11800000
-#define	AC97_PHYS_ADDR		0x10000000
-#define	USBH_PHYS_ADDR		0x10100000
-#define	USBD_PHYS_ADDR		0x10200000
-#define	IRDA_PHYS_ADDR		0x10300000
-#define	MAC0_PHYS_ADDR		0x10500000
-#define	MACEN_PHYS_ADDR		0x10520000
-#define	MACDMA0_PHYS_ADDR	0x14004000
-#define	MACDMA1_PHYS_ADDR	0x14004200
-#define	I2S_PHYS_ADDR		0x11000000
-#define	UART0_PHYS_ADDR		0x11100000
-#define	UART1_PHYS_ADDR		0x11200000
-#define	UART3_PHYS_ADDR		0x11400000
-#define	SSI0_PHYS_ADDR		0x11600000
-#define	SSI1_PHYS_ADDR		0x11680000
-#define GPIO2_PHYS_ADDR		0x11700000
-#define	SYS_PHYS_ADDR		0x11900000
-#define LCD_PHYS_ADDR		0x15000000
-#define PCMCIA_IO_PHYS_ADDR	0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR	0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR	0xF80000000ULL
-#endif
-
-/***********************************************************************/
-
-#ifdef CONFIG_SOC_AU1550
-#define	MEM_PHYS_ADDR		0x14000000
-#define	STATIC_MEM_PHYS_ADDR	0x14001000
-#define	IC0_PHYS_ADDR		0x10400000
-#define	IC1_PHYS_ADDR		0x11800000
-#define	USBH_PHYS_ADDR		0x14020000
-#define	USBD_PHYS_ADDR		0x10200000
-#define PCI_PHYS_ADDR		0x14005000
-#define	MAC0_PHYS_ADDR		0x10500000
-#define	MAC1_PHYS_ADDR		0x10510000
-#define	MACEN_PHYS_ADDR		0x10520000
-#define	MACDMA0_PHYS_ADDR	0x14004000
-#define	MACDMA1_PHYS_ADDR	0x14004200
-#define	UART0_PHYS_ADDR		0x11100000
-#define	UART1_PHYS_ADDR		0x11200000
-#define	UART3_PHYS_ADDR		0x11400000
-#define GPIO2_PHYS_ADDR		0x11700000
-#define	SYS_PHYS_ADDR		0x11900000
-#define	DDMA_PHYS_ADDR		0x14002000
-#define PE_PHYS_ADDR		0x14008000
-#define PSC0_PHYS_ADDR		0x11A00000
-#define PSC1_PHYS_ADDR		0x11B00000
-#define PSC2_PHYS_ADDR		0x10A00000
-#define PSC3_PHYS_ADDR		0x10B00000
-#define PCI_MEM_PHYS_ADDR	0x400000000ULL
-#define PCI_IO_PHYS_ADDR	0x500000000ULL
-#define PCI_CONFIG0_PHYS_ADDR	0x600000000ULL
-#define PCI_CONFIG1_PHYS_ADDR	0x680000000ULL
-#define PCMCIA_IO_PHYS_ADDR	0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR	0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR	0xF80000000ULL
-#endif
-
-/***********************************************************************/
-
-#ifdef CONFIG_SOC_AU1200
-#define	MEM_PHYS_ADDR		0x14000000
-#define	STATIC_MEM_PHYS_ADDR	0x14001000
-#define AES_PHYS_ADDR		0x10300000
-#define CIM_PHYS_ADDR		0x14004000
-#define	IC0_PHYS_ADDR		0x10400000
-#define	IC1_PHYS_ADDR		0x11800000
-#define USBM_PHYS_ADDR		0x14020000
-#define	USBH_PHYS_ADDR		0x14020100
-#define	UART0_PHYS_ADDR		0x11100000
-#define	UART1_PHYS_ADDR		0x11200000
-#define GPIO2_PHYS_ADDR		0x11700000
-#define	SYS_PHYS_ADDR		0x11900000
-#define	DDMA_PHYS_ADDR		0x14002000
-#define PSC0_PHYS_ADDR	 	0x11A00000
-#define PSC1_PHYS_ADDR	 	0x11B00000
-#define SD0_PHYS_ADDR		0x10600000
-#define SD1_PHYS_ADDR		0x10680000
-#define LCD_PHYS_ADDR		0x15000000
-#define SWCNT_PHYS_ADDR		0x1110010C
-#define MAEFE_PHYS_ADDR		0x14012000
-#define MAEBE_PHYS_ADDR		0x14010000
-#define PCMCIA_IO_PHYS_ADDR	0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR	0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR	0xF80000000ULL
-#endif
-
-/* Static Bus Controller */
-#define MEM_STCFG0		0xB4001000
-#define MEM_STTIME0		0xB4001004
-#define MEM_STADDR0		0xB4001008
-
-#define MEM_STCFG1		0xB4001010
-#define MEM_STTIME1		0xB4001014
-#define MEM_STADDR1		0xB4001018
-
-#define MEM_STCFG2		0xB4001020
-#define MEM_STTIME2		0xB4001024
-#define MEM_STADDR2		0xB4001028
-
-#define MEM_STCFG3		0xB4001030
-#define MEM_STTIME3		0xB4001034
-#define MEM_STADDR3		0xB4001038
-
-#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-#define MEM_STNDCTL		0xB4001100
-#define MEM_STSTAT		0xB4001104
-
-#define MEM_STNAND_CMD		0x0
-#define MEM_STNAND_ADDR 	0x4
-#define MEM_STNAND_DATA 	0x20
-#endif
-
-/* Interrupt Controller 0 */
-#define IC0_CFG0RD		0xB0400040
-#define IC0_CFG0SET		0xB0400040
-#define IC0_CFG0CLR		0xB0400044
-
-#define IC0_CFG1RD		0xB0400048
-#define IC0_CFG1SET		0xB0400048
-#define IC0_CFG1CLR		0xB040004C
-
-#define IC0_CFG2RD		0xB0400050
-#define IC0_CFG2SET		0xB0400050
-#define IC0_CFG2CLR		0xB0400054
-
-#define IC0_REQ0INT		0xB0400054
-#define IC0_SRCRD		0xB0400058
-#define IC0_SRCSET		0xB0400058
-#define IC0_SRCCLR		0xB040005C
-#define IC0_REQ1INT		0xB040005C
-
-#define IC0_ASSIGNRD		0xB0400060
-#define IC0_ASSIGNSET		0xB0400060
-#define IC0_ASSIGNCLR		0xB0400064
-
-#define IC0_WAKERD		0xB0400068
-#define IC0_WAKESET		0xB0400068
-#define IC0_WAKECLR		0xB040006C
-
-#define IC0_MASKRD		0xB0400070
-#define IC0_MASKSET		0xB0400070
-#define IC0_MASKCLR		0xB0400074
-
-#define IC0_RISINGRD		0xB0400078
-#define IC0_RISINGCLR		0xB0400078
-#define IC0_FALLINGRD		0xB040007C
-#define IC0_FALLINGCLR		0xB040007C
-
-#define IC0_TESTBIT		0xB0400080
-
-/* Interrupt Controller 1 */
-#define IC1_CFG0RD		0xB1800040
-#define IC1_CFG0SET		0xB1800040
-#define IC1_CFG0CLR		0xB1800044
-
-#define IC1_CFG1RD		0xB1800048
-#define IC1_CFG1SET		0xB1800048
-#define IC1_CFG1CLR		0xB180004C
-
-#define IC1_CFG2RD		0xB1800050
-#define IC1_CFG2SET		0xB1800050
-#define IC1_CFG2CLR		0xB1800054
-
-#define IC1_REQ0INT		0xB1800054
-#define IC1_SRCRD		0xB1800058
-#define IC1_SRCSET		0xB1800058
-#define IC1_SRCCLR		0xB180005C
-#define IC1_REQ1INT		0xB180005C
-
-#define IC1_ASSIGNRD            0xB1800060
-#define IC1_ASSIGNSET           0xB1800060
-#define IC1_ASSIGNCLR           0xB1800064
-
-#define IC1_WAKERD		0xB1800068
-#define IC1_WAKESET		0xB1800068
-#define IC1_WAKECLR		0xB180006C
-
-#define IC1_MASKRD		0xB1800070
-#define IC1_MASKSET		0xB1800070
-#define IC1_MASKCLR		0xB1800074
-
-#define IC1_RISINGRD		0xB1800078
-#define IC1_RISINGCLR		0xB1800078
-#define IC1_FALLINGRD		0xB180007C
-#define IC1_FALLINGCLR		0xB180007C
-
-#define IC1_TESTBIT		0xB1800080
-
-/* Interrupt Configuration Modes */
-#define INTC_INT_DISABLED		0x0
-#define INTC_INT_RISE_EDGE		0x1
-#define INTC_INT_FALL_EDGE		0x2
-#define INTC_INT_RISE_AND_FALL_EDGE	0x3
-#define INTC_INT_HIGH_LEVEL		0x5
-#define INTC_INT_LOW_LEVEL		0x6
-#define INTC_INT_HIGH_AND_LOW_LEVEL	0x7
-
-/* Interrupt Numbers */
-/* Au1000 */
-#ifdef CONFIG_SOC_AU1000
-enum soc_au1000_ints {
-	AU1000_FIRST_INT	= MIPS_CPU_IRQ_BASE + 8,
-	AU1000_UART0_INT	= AU1000_FIRST_INT,
-	AU1000_UART1_INT,				/* au1000 */
-	AU1000_UART2_INT,				/* au1000 */
-	AU1000_UART3_INT,
-	AU1000_SSI0_INT,				/* au1000 */
-	AU1000_SSI1_INT,				/* au1000 */
-	AU1000_DMA_INT_BASE,
-
-	AU1000_TOY_INT		= AU1000_FIRST_INT + 14,
-	AU1000_TOY_MATCH0_INT,
-	AU1000_TOY_MATCH1_INT,
-	AU1000_TOY_MATCH2_INT,
-	AU1000_RTC_INT,
-	AU1000_RTC_MATCH0_INT,
-	AU1000_RTC_MATCH1_INT,
-	AU1000_RTC_MATCH2_INT,
-	AU1000_IRDA_TX_INT,				/* au1000 */
-	AU1000_IRDA_RX_INT,				/* au1000 */
-	AU1000_USB_DEV_REQ_INT,
-	AU1000_USB_DEV_SUS_INT,
-	AU1000_USB_HOST_INT,
-	AU1000_ACSYNC_INT,
-	AU1000_MAC0_DMA_INT,
-	AU1000_MAC1_DMA_INT,
-	AU1000_I2S_UO_INT,				/* au1000 */
-	AU1000_AC97C_INT,
-	AU1000_GPIO_0,
-	AU1000_GPIO_1,
-	AU1000_GPIO_2,
-	AU1000_GPIO_3,
-	AU1000_GPIO_4,
-	AU1000_GPIO_5,
-	AU1000_GPIO_6,
-	AU1000_GPIO_7,
-	AU1000_GPIO_8,
-	AU1000_GPIO_9,
-	AU1000_GPIO_10,
-	AU1000_GPIO_11,
-	AU1000_GPIO_12,
-	AU1000_GPIO_13,
-	AU1000_GPIO_14,
-	AU1000_GPIO_15,
-	AU1000_GPIO_16,
-	AU1000_GPIO_17,
-	AU1000_GPIO_18,
-	AU1000_GPIO_19,
-	AU1000_GPIO_20,
-	AU1000_GPIO_21,
-	AU1000_GPIO_22,
-	AU1000_GPIO_23,
-	AU1000_GPIO_24,
-	AU1000_GPIO_25,
-	AU1000_GPIO_26,
-	AU1000_GPIO_27,
-	AU1000_GPIO_28,
-	AU1000_GPIO_29,
-	AU1000_GPIO_30,
-	AU1000_GPIO_31,
-};
-
-#define UART0_ADDR		0xB1100000
-#define UART1_ADDR		0xB1200000
-#define UART2_ADDR		0xB1300000
-#define UART3_ADDR		0xB1400000
-
-#define USB_OHCI_BASE		0x10100000	/* phys addr for ioremap */
-#define USB_HOST_CONFIG 	0xB017FFFC
-
-#define AU1000_ETH0_BASE	0xB0500000
-#define AU1000_ETH1_BASE	0xB0510000
-#define AU1000_MAC0_ENABLE	0xB0520000
-#define AU1000_MAC1_ENABLE	0xB0520004
-#define NUM_ETH_INTERFACES 2
-#endif /* CONFIG_SOC_AU1000 */
-
-/* Au1500 */
-#ifdef CONFIG_SOC_AU1500
-enum soc_au1500_ints {
-	AU1500_FIRST_INT	= MIPS_CPU_IRQ_BASE + 8,
-	AU1500_UART0_INT	= AU1500_FIRST_INT,
-	AU1000_PCI_INTA,				/* au1500 */
-	AU1000_PCI_INTB,				/* au1500 */
-	AU1500_UART3_INT,
-	AU1000_PCI_INTC,				/* au1500 */
-	AU1000_PCI_INTD,				/* au1500 */
-	AU1000_DMA_INT_BASE,
-
-	AU1000_TOY_INT		= AU1500_FIRST_INT + 14,
-	AU1000_TOY_MATCH0_INT,
-	AU1000_TOY_MATCH1_INT,
-	AU1000_TOY_MATCH2_INT,
-	AU1000_RTC_INT,
-	AU1000_RTC_MATCH0_INT,
-	AU1000_RTC_MATCH1_INT,
-	AU1000_RTC_MATCH2_INT,
-	AU1500_PCI_ERR_INT,
-	AU1500_RESERVED_INT,
-	AU1000_USB_DEV_REQ_INT,
-	AU1000_USB_DEV_SUS_INT,
-	AU1000_USB_HOST_INT,
-	AU1000_ACSYNC_INT,
-	AU1500_MAC0_DMA_INT,
-	AU1500_MAC1_DMA_INT,
-	AU1000_AC97C_INT	= AU1500_FIRST_INT + 31,
-	AU1000_GPIO_0,
-	AU1000_GPIO_1,
-	AU1000_GPIO_2,
-	AU1000_GPIO_3,
-	AU1000_GPIO_4,
-	AU1000_GPIO_5,
-	AU1000_GPIO_6,
-	AU1000_GPIO_7,
-	AU1000_GPIO_8,
-	AU1000_GPIO_9,
-	AU1000_GPIO_10,
-	AU1000_GPIO_11,
-	AU1000_GPIO_12,
-	AU1000_GPIO_13,
-	AU1000_GPIO_14,
-	AU1000_GPIO_15,
-	AU1500_GPIO_200,
-	AU1500_GPIO_201,
-	AU1500_GPIO_202,
-	AU1500_GPIO_203,
-	AU1500_GPIO_20,
-	AU1500_GPIO_204,
-	AU1500_GPIO_205,
-	AU1500_GPIO_23,
-	AU1500_GPIO_24,
-	AU1500_GPIO_25,
-	AU1500_GPIO_26,
-	AU1500_GPIO_27,
-	AU1500_GPIO_28,
-	AU1500_GPIO_206,
-	AU1500_GPIO_207,
-	AU1500_GPIO_208_215,
-};
-
-/* shortcuts */
-#define INTA AU1000_PCI_INTA
-#define INTB AU1000_PCI_INTB
-#define INTC AU1000_PCI_INTC
-#define INTD AU1000_PCI_INTD
-
-#define UART0_ADDR		0xB1100000
-#define UART3_ADDR		0xB1400000
-
-#define USB_OHCI_BASE		0x10100000	/* phys addr for ioremap */
-#define USB_HOST_CONFIG 	0xB017fffc
-
-#define AU1500_ETH0_BASE	0xB1500000
-#define AU1500_ETH1_BASE	0xB1510000
-#define AU1500_MAC0_ENABLE	0xB1520000
-#define AU1500_MAC1_ENABLE	0xB1520004
-#define NUM_ETH_INTERFACES 2
-#endif /* CONFIG_SOC_AU1500 */
-
-/* Au1100 */
-#ifdef CONFIG_SOC_AU1100
-enum soc_au1100_ints {
-	AU1100_FIRST_INT	= MIPS_CPU_IRQ_BASE + 8,
-	AU1100_UART0_INT,
-	AU1100_UART1_INT,
-	AU1100_SD_INT,
-	AU1100_UART3_INT,
-	AU1000_SSI0_INT,
-	AU1000_SSI1_INT,
-	AU1000_DMA_INT_BASE,
-
-	AU1000_TOY_INT		= AU1100_FIRST_INT + 14,
-	AU1000_TOY_MATCH0_INT,
-	AU1000_TOY_MATCH1_INT,
-	AU1000_TOY_MATCH2_INT,
-	AU1000_RTC_INT,
-	AU1000_RTC_MATCH0_INT,
-	AU1000_RTC_MATCH1_INT,
-	AU1000_RTC_MATCH2_INT,
-	AU1000_IRDA_TX_INT,
-	AU1000_IRDA_RX_INT,
-	AU1000_USB_DEV_REQ_INT,
-	AU1000_USB_DEV_SUS_INT,
-	AU1000_USB_HOST_INT,
-	AU1000_ACSYNC_INT,
-	AU1100_MAC0_DMA_INT,
-	AU1100_GPIO_208_215,
-	AU1100_LCD_INT,
-	AU1000_AC97C_INT,
-	AU1000_GPIO_0,
-	AU1000_GPIO_1,
-	AU1000_GPIO_2,
-	AU1000_GPIO_3,
-	AU1000_GPIO_4,
-	AU1000_GPIO_5,
-	AU1000_GPIO_6,
-	AU1000_GPIO_7,
-	AU1000_GPIO_8,
-	AU1000_GPIO_9,
-	AU1000_GPIO_10,
-	AU1000_GPIO_11,
-	AU1000_GPIO_12,
-	AU1000_GPIO_13,
-	AU1000_GPIO_14,
-	AU1000_GPIO_15,
-	AU1000_GPIO_16,
-	AU1000_GPIO_17,
-	AU1000_GPIO_18,
-	AU1000_GPIO_19,
-	AU1000_GPIO_20,
-	AU1000_GPIO_21,
-	AU1000_GPIO_22,
-	AU1000_GPIO_23,
-	AU1000_GPIO_24,
-	AU1000_GPIO_25,
-	AU1000_GPIO_26,
-	AU1000_GPIO_27,
-	AU1000_GPIO_28,
-	AU1000_GPIO_29,
-	AU1000_GPIO_30,
-	AU1000_GPIO_31,
-};
-
-#define UART0_ADDR		0xB1100000
-#define UART1_ADDR		0xB1200000
-#define UART3_ADDR		0xB1400000
-
-#define USB_OHCI_BASE		0x10100000	/* phys addr for ioremap */
-#define USB_HOST_CONFIG 	0xB017FFFC
-
-#define AU1100_ETH0_BASE	0xB0500000
-#define AU1100_MAC0_ENABLE	0xB0520000
-#define NUM_ETH_INTERFACES 1
-#endif /* CONFIG_SOC_AU1100 */
-
-#ifdef CONFIG_SOC_AU1550
-enum soc_au1550_ints {
-	AU1550_FIRST_INT	= MIPS_CPU_IRQ_BASE + 8,
-	AU1550_UART0_INT	= AU1550_FIRST_INT,
-	AU1550_PCI_INTA,
-	AU1550_PCI_INTB,
-	AU1550_DDMA_INT,
-	AU1550_CRYPTO_INT,
-	AU1550_PCI_INTC,
-	AU1550_PCI_INTD,
-	AU1550_PCI_RST_INT,
-	AU1550_UART1_INT,
-	AU1550_UART3_INT,
-	AU1550_PSC0_INT,
-	AU1550_PSC1_INT,
-	AU1550_PSC2_INT,
-	AU1550_PSC3_INT,
-	AU1000_TOY_INT,
-	AU1000_TOY_MATCH0_INT,
-	AU1000_TOY_MATCH1_INT,
-	AU1000_TOY_MATCH2_INT,
-	AU1000_RTC_INT,
-	AU1000_RTC_MATCH0_INT,
-	AU1000_RTC_MATCH1_INT,
-	AU1000_RTC_MATCH2_INT,
-
-	AU1550_NAND_INT			= AU1550_FIRST_INT + 23,
-	AU1550_USB_DEV_REQ_INT,
-	AU1000_USB_DEV_REQ_INT		= AU1550_USB_DEV_REQ_INT,
-	AU1550_USB_DEV_SUS_INT,
-	AU1000_USB_DEV_SUS_INT		= AU1550_USB_DEV_SUS_INT,
-	AU1550_USB_HOST_INT,
-	AU1000_USB_HOST_INT		= AU1550_USB_HOST_INT,
-	AU1550_MAC0_DMA_INT,
-	AU1550_MAC1_DMA_INT,
-	AU1000_GPIO_0			= AU1550_FIRST_INT + 32,
-	AU1000_GPIO_1,
-	AU1000_GPIO_2,
-	AU1000_GPIO_3,
-	AU1000_GPIO_4,
-	AU1000_GPIO_5,
-	AU1000_GPIO_6,
-	AU1000_GPIO_7,
-	AU1000_GPIO_8,
-	AU1000_GPIO_9,
-	AU1000_GPIO_10,
-	AU1000_GPIO_11,
-	AU1000_GPIO_12,
-	AU1000_GPIO_13,
-	AU1000_GPIO_14,
-	AU1000_GPIO_15,
-	AU1550_GPIO_200,
-	AU1500_GPIO_201_205,			/* Logical or of GPIO201:205 */
-	AU1500_GPIO_16,
-	AU1500_GPIO_17,
-	AU1500_GPIO_20,
-	AU1500_GPIO_21,
-	AU1500_GPIO_22,
-	AU1500_GPIO_23,
-	AU1500_GPIO_24,
-	AU1500_GPIO_25,
-	AU1500_GPIO_26,
-	AU1500_GPIO_27,
-	AU1500_GPIO_28,
-	AU1500_GPIO_206,
-	AU1500_GPIO_207,
-	AU1500_GPIO_208_218,			/* Logical or of GPIO208:218 */
-};
-
-/* shortcuts */
-#define INTA AU1550_PCI_INTA
-#define INTB AU1550_PCI_INTB
-#define INTC AU1550_PCI_INTC
-#define INTD AU1550_PCI_INTD
-
-#define UART0_ADDR		0xB1100000
-#define UART1_ADDR		0xB1200000
-#define UART3_ADDR		0xB1400000
-
-#define USB_OHCI_BASE		0x14020000	/* phys addr for ioremap */
-#define USB_OHCI_LEN		0x00060000
-#define USB_HOST_CONFIG 	0xB4027ffc
-
-#define AU1550_ETH0_BASE	0xB0500000
-#define AU1550_ETH1_BASE	0xB0510000
-#define AU1550_MAC0_ENABLE	0xB0520000
-#define AU1550_MAC1_ENABLE	0xB0520004
-#define NUM_ETH_INTERFACES 2
-#endif /* CONFIG_SOC_AU1550 */
-
-#ifdef CONFIG_SOC_AU1200
-enum soc_au1200_ints {
-	AU1200_FIRST_INT	= MIPS_CPU_IRQ_BASE + 8,
-	AU1200_UART0_INT	= AU1200_FIRST_INT,
-	AU1200_SWT_INT,
-	AU1200_SD_INT,
-	AU1200_DDMA_INT,
-	AU1200_MAE_BE_INT,
-	AU1200_GPIO_200,
-	AU1200_GPIO_201,
-	AU1200_GPIO_202,
-	AU1200_UART1_INT,
-	AU1200_MAE_FE_INT,
-	AU1200_PSC0_INT,
-	AU1200_PSC1_INT,
-	AU1200_AES_INT,
-	AU1200_CAMERA_INT,
-	AU1000_TOY_INT,
-	AU1000_TOY_MATCH0_INT,
-	AU1000_TOY_MATCH1_INT,
-	AU1000_TOY_MATCH2_INT,
-	AU1000_RTC_INT,
-	AU1000_RTC_MATCH0_INT,
-	AU1000_RTC_MATCH1_INT,
-	AU1000_RTC_MATCH2_INT,
-
-	AU1200_NAND_INT		= AU1200_FIRST_INT + 23,
-	AU1200_GPIO_204,
-	AU1200_GPIO_205,
-	AU1200_GPIO_206,
-	AU1200_GPIO_207,
-	AU1200_GPIO_208_215,			/* Logical OR of 208:215 */
-	AU1200_USB_INT,
-	AU1000_USB_HOST_INT	= AU1200_USB_INT,
-	AU1200_LCD_INT,
-	AU1200_MAE_BOTH_INT,
-	AU1000_GPIO_0,
-	AU1000_GPIO_1,
-	AU1000_GPIO_2,
-	AU1000_GPIO_3,
-	AU1000_GPIO_4,
-	AU1000_GPIO_5,
-	AU1000_GPIO_6,
-	AU1000_GPIO_7,
-	AU1000_GPIO_8,
-	AU1000_GPIO_9,
-	AU1000_GPIO_10,
-	AU1000_GPIO_11,
-	AU1000_GPIO_12,
-	AU1000_GPIO_13,
-	AU1000_GPIO_14,
-	AU1000_GPIO_15,
-	AU1000_GPIO_16,
-	AU1000_GPIO_17,
-	AU1000_GPIO_18,
-	AU1000_GPIO_19,
-	AU1000_GPIO_20,
-	AU1000_GPIO_21,
-	AU1000_GPIO_22,
-	AU1000_GPIO_23,
-	AU1000_GPIO_24,
-	AU1000_GPIO_25,
-	AU1000_GPIO_26,
-	AU1000_GPIO_27,
-	AU1000_GPIO_28,
-	AU1000_GPIO_29,
-	AU1000_GPIO_30,
-	AU1000_GPIO_31,
-};
-
-#define UART0_ADDR		0xB1100000
-#define UART1_ADDR		0xB1200000
-
-#define USB_UOC_BASE		0x14020020
-#define USB_UOC_LEN		0x20
-#define USB_OHCI_BASE		0x14020100
-#define USB_OHCI_LEN		0x100
-#define USB_EHCI_BASE		0x14020200
-#define USB_EHCI_LEN		0x100
-#define USB_UDC_BASE		0x14022000
-#define USB_UDC_LEN		0x2000
-#define USB_MSR_BASE		0xB4020000
-#define USB_MSR_MCFG		4
-#define USBMSRMCFG_OMEMEN	0
-#define USBMSRMCFG_OBMEN	1
-#define USBMSRMCFG_EMEMEN	2
-#define USBMSRMCFG_EBMEN	3
-#define USBMSRMCFG_DMEMEN	4
-#define USBMSRMCFG_DBMEN	5
-#define USBMSRMCFG_GMEMEN	6
-#define USBMSRMCFG_OHCCLKEN	16
-#define USBMSRMCFG_EHCCLKEN	17
-#define USBMSRMCFG_UDCCLKEN	18
-#define USBMSRMCFG_PHYPLLEN	19
-#define USBMSRMCFG_RDCOMB	30
-#define USBMSRMCFG_PFEN 	31
-
-#endif /* CONFIG_SOC_AU1200 */
-
-#define AU1000_INTC0_INT_BASE	(MIPS_CPU_IRQ_BASE + 8)
-#define AU1000_INTC0_INT_LAST	(AU1000_INTC0_INT_BASE + 31)
-#define AU1000_INTC1_INT_BASE	(AU1000_INTC0_INT_BASE + 32)
-#define AU1000_INTC1_INT_LAST	(AU1000_INTC1_INT_BASE + 31)
-
-#define AU1000_MAX_INTR 	AU1000_INTC1_INT_LAST
-#define INTX			0xFF			/* not valid */
-
-/* Programmable Counters 0 and 1 */
-#define SYS_BASE		0xB1900000
-#define SYS_COUNTER_CNTRL	(SYS_BASE + 0x14)
-#  define SYS_CNTRL_E1S 	(1 << 23)
-#  define SYS_CNTRL_T1S 	(1 << 20)
-#  define SYS_CNTRL_M21 	(1 << 19)
-#  define SYS_CNTRL_M11 	(1 << 18)
-#  define SYS_CNTRL_M01 	(1 << 17)
-#  define SYS_CNTRL_C1S 	(1 << 16)
-#  define SYS_CNTRL_BP		(1 << 14)
-#  define SYS_CNTRL_EN1 	(1 << 13)
-#  define SYS_CNTRL_BT1 	(1 << 12)
-#  define SYS_CNTRL_EN0 	(1 << 11)
-#  define SYS_CNTRL_BT0 	(1 << 10)
-#  define SYS_CNTRL_E0		(1 << 8)
-#  define SYS_CNTRL_E0S 	(1 << 7)
-#  define SYS_CNTRL_32S 	(1 << 5)
-#  define SYS_CNTRL_T0S 	(1 << 4)
-#  define SYS_CNTRL_M20 	(1 << 3)
-#  define SYS_CNTRL_M10 	(1 << 2)
-#  define SYS_CNTRL_M00 	(1 << 1)
-#  define SYS_CNTRL_C0S 	(1 << 0)
-
-/* Programmable Counter 0 Registers */
-#define SYS_TOYTRIM		(SYS_BASE + 0)
-#define SYS_TOYWRITE		(SYS_BASE + 4)
-#define SYS_TOYMATCH0		(SYS_BASE + 8)
-#define SYS_TOYMATCH1		(SYS_BASE + 0xC)
-#define SYS_TOYMATCH2		(SYS_BASE + 0x10)
-#define SYS_TOYREAD		(SYS_BASE + 0x40)
-
-/* Programmable Counter 1 Registers */
-#define SYS_RTCTRIM		(SYS_BASE + 0x44)
-#define SYS_RTCWRITE		(SYS_BASE + 0x48)
-#define SYS_RTCMATCH0		(SYS_BASE + 0x4C)
-#define SYS_RTCMATCH1		(SYS_BASE + 0x50)
-#define SYS_RTCMATCH2		(SYS_BASE + 0x54)
-#define SYS_RTCREAD		(SYS_BASE + 0x58)
-
-/* I2S Controller */
-#define I2S_DATA		0xB1000000
-#  define I2S_DATA_MASK 	0xffffff
-#define I2S_CONFIG		0xB1000004
-#  define I2S_CONFIG_XU 	(1 << 25)
-#  define I2S_CONFIG_XO 	(1 << 24)
-#  define I2S_CONFIG_RU 	(1 << 23)
-#  define I2S_CONFIG_RO 	(1 << 22)
-#  define I2S_CONFIG_TR 	(1 << 21)
-#  define I2S_CONFIG_TE 	(1 << 20)
-#  define I2S_CONFIG_TF 	(1 << 19)
-#  define I2S_CONFIG_RR 	(1 << 18)
-#  define I2S_CONFIG_RE 	(1 << 17)
-#  define I2S_CONFIG_RF 	(1 << 16)
-#  define I2S_CONFIG_PD 	(1 << 11)
-#  define I2S_CONFIG_LB 	(1 << 10)
-#  define I2S_CONFIG_IC 	(1 << 9)
-#  define I2S_CONFIG_FM_BIT	7
-#  define I2S_CONFIG_FM_MASK	(0x3 << I2S_CONFIG_FM_BIT)
-#    define I2S_CONFIG_FM_I2S	(0x0 << I2S_CONFIG_FM_BIT)
-#    define I2S_CONFIG_FM_LJ	(0x1 << I2S_CONFIG_FM_BIT)
-#    define I2S_CONFIG_FM_RJ	(0x2 << I2S_CONFIG_FM_BIT)
-#  define I2S_CONFIG_TN 	(1 << 6)
-#  define I2S_CONFIG_RN 	(1 << 5)
-#  define I2S_CONFIG_SZ_BIT	0
-#  define I2S_CONFIG_SZ_MASK	(0x1F << I2S_CONFIG_SZ_BIT)
-
-#define I2S_CONTROL		0xB1000008
-#  define I2S_CONTROL_D 	(1 << 1)
-#  define I2S_CONTROL_CE	(1 << 0)
-
-/* USB Host Controller */
-#ifndef USB_OHCI_LEN
-#define USB_OHCI_LEN		0x00100000
-#endif
-
-#ifndef CONFIG_SOC_AU1200
-
-/* USB Device Controller */
-#define USBD_EP0RD		0xB0200000
-#define USBD_EP0WR		0xB0200004
-#define USBD_EP2WR		0xB0200008
-#define USBD_EP3WR		0xB020000C
-#define USBD_EP4RD		0xB0200010
-#define USBD_EP5RD		0xB0200014
-#define USBD_INTEN		0xB0200018
-#define USBD_INTSTAT		0xB020001C
-#  define USBDEV_INT_SOF	(1 << 12)
-#  define USBDEV_INT_HF_BIT	6
-#  define USBDEV_INT_HF_MASK	(0x3f << USBDEV_INT_HF_BIT)
-#  define USBDEV_INT_CMPLT_BIT	0
-#  define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
-#define USBD_CONFIG		0xB0200020
-#define USBD_EP0CS		0xB0200024
-#define USBD_EP2CS		0xB0200028
-#define USBD_EP3CS		0xB020002C
-#define USBD_EP4CS		0xB0200030
-#define USBD_EP5CS		0xB0200034
-#  define USBDEV_CS_SU		(1 << 14)
-#  define USBDEV_CS_NAK 	(1 << 13)
-#  define USBDEV_CS_ACK 	(1 << 12)
-#  define USBDEV_CS_BUSY	(1 << 11)
-#  define USBDEV_CS_TSIZE_BIT	1
-#  define USBDEV_CS_TSIZE_MASK	(0x3ff << USBDEV_CS_TSIZE_BIT)
-#  define USBDEV_CS_STALL	(1 << 0)
-#define USBD_EP0RDSTAT		0xB0200040
-#define USBD_EP0WRSTAT		0xB0200044
-#define USBD_EP2WRSTAT		0xB0200048
-#define USBD_EP3WRSTAT		0xB020004C
-#define USBD_EP4RDSTAT		0xB0200050
-#define USBD_EP5RDSTAT		0xB0200054
-#  define USBDEV_FSTAT_FLUSH	(1 << 6)
-#  define USBDEV_FSTAT_UF	(1 << 5)
-#  define USBDEV_FSTAT_OF	(1 << 4)
-#  define USBDEV_FSTAT_FCNT_BIT 0
-#  define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
-#define USBD_ENABLE		0xB0200058
-#  define USBDEV_ENABLE 	(1 << 1)
-#  define USBDEV_CE		(1 << 0)
-
-#endif /* !CONFIG_SOC_AU1200 */
-
-/* Ethernet Controllers  */
-
-/* 4 byte offsets from AU1000_ETH_BASE */
-#define MAC_CONTROL		0x0
-#  define MAC_RX_ENABLE 	(1 << 2)
-#  define MAC_TX_ENABLE 	(1 << 3)
-#  define MAC_DEF_CHECK 	(1 << 5)
-#  define MAC_SET_BL(X) 	(((X) & 0x3) << 6)
-#  define MAC_AUTO_PAD		(1 << 8)
-#  define MAC_DISABLE_RETRY	(1 << 10)
-#  define MAC_DISABLE_BCAST	(1 << 11)
-#  define MAC_LATE_COL		(1 << 12)
-#  define MAC_HASH_MODE 	(1 << 13)
-#  define MAC_HASH_ONLY 	(1 << 15)
-#  define MAC_PASS_ALL		(1 << 16)
-#  define MAC_INVERSE_FILTER	(1 << 17)
-#  define MAC_PROMISCUOUS	(1 << 18)
-#  define MAC_PASS_ALL_MULTI	(1 << 19)
-#  define MAC_FULL_DUPLEX	(1 << 20)
-#  define MAC_NORMAL_MODE	0
-#  define MAC_INT_LOOPBACK	(1 << 21)
-#  define MAC_EXT_LOOPBACK	(1 << 22)
-#  define MAC_DISABLE_RX_OWN	(1 << 23)
-#  define MAC_BIG_ENDIAN	(1 << 30)
-#  define MAC_RX_ALL		(1 << 31)
-#define MAC_ADDRESS_HIGH	0x4
-#define MAC_ADDRESS_LOW		0x8
-#define MAC_MCAST_HIGH		0xC
-#define MAC_MCAST_LOW		0x10
-#define MAC_MII_CNTRL		0x14
-#  define MAC_MII_BUSY		(1 << 0)
-#  define MAC_MII_READ		0
-#  define MAC_MII_WRITE		(1 << 1)
-#  define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
-#  define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
-#define MAC_MII_DATA		0x18
-#define MAC_FLOW_CNTRL		0x1C
-#  define MAC_FLOW_CNTRL_BUSY	(1 << 0)
-#  define MAC_FLOW_CNTRL_ENABLE (1 << 1)
-#  define MAC_PASS_CONTROL	(1 << 2)
-#  define MAC_SET_PAUSE(X)	(((X) & 0xffff) << 16)
-#define MAC_VLAN1_TAG		0x20
-#define MAC_VLAN2_TAG		0x24
-
-/* Ethernet Controller Enable */
-
-#  define MAC_EN_CLOCK_ENABLE	(1 << 0)
-#  define MAC_EN_RESET0		(1 << 1)
-#  define MAC_EN_TOSS		(0 << 2)
-#  define MAC_EN_CACHEABLE	(1 << 3)
-#  define MAC_EN_RESET1 	(1 << 4)
-#  define MAC_EN_RESET2 	(1 << 5)
-#  define MAC_DMA_RESET 	(1 << 6)
-
-/* Ethernet Controller DMA Channels */
-
-#define MAC0_TX_DMA_ADDR	0xB4004000
-#define MAC1_TX_DMA_ADDR	0xB4004200
-/* offsets from MAC_TX_RING_ADDR address */
-#define MAC_TX_BUFF0_STATUS	0x0
-#  define TX_FRAME_ABORTED	(1 << 0)
-#  define TX_JAB_TIMEOUT	(1 << 1)
-#  define TX_NO_CARRIER 	(1 << 2)
-#  define TX_LOSS_CARRIER	(1 << 3)
-#  define TX_EXC_DEF		(1 << 4)
-#  define TX_LATE_COLL_ABORT	(1 << 5)
-#  define TX_EXC_COLL		(1 << 6)
-#  define TX_UNDERRUN		(1 << 7)
-#  define TX_DEFERRED		(1 << 8)
-#  define TX_LATE_COLL		(1 << 9)
-#  define TX_COLL_CNT_MASK	(0xF << 10)
-#  define TX_PKT_RETRY		(1 << 31)
-#define MAC_TX_BUFF0_ADDR	0x4
-#  define TX_DMA_ENABLE 	(1 << 0)
-#  define TX_T_DONE		(1 << 1)
-#  define TX_GET_DMA_BUFFER(X)	(((X) >> 2) & 0x3)
-#define MAC_TX_BUFF0_LEN	0x8
-#define MAC_TX_BUFF1_STATUS	0x10
-#define MAC_TX_BUFF1_ADDR	0x14
-#define MAC_TX_BUFF1_LEN	0x18
-#define MAC_TX_BUFF2_STATUS	0x20
-#define MAC_TX_BUFF2_ADDR	0x24
-#define MAC_TX_BUFF2_LEN	0x28
-#define MAC_TX_BUFF3_STATUS	0x30
-#define MAC_TX_BUFF3_ADDR	0x34
-#define MAC_TX_BUFF3_LEN	0x38
-
-#define MAC0_RX_DMA_ADDR	0xB4004100
-#define MAC1_RX_DMA_ADDR	0xB4004300
-/* offsets from MAC_RX_RING_ADDR */
-#define MAC_RX_BUFF0_STATUS	0x0
-#  define RX_FRAME_LEN_MASK	0x3fff
-#  define RX_WDOG_TIMER 	(1 << 14)
-#  define RX_RUNT		(1 << 15)
-#  define RX_OVERLEN		(1 << 16)
-#  define RX_COLL		(1 << 17)
-#  define RX_ETHER		(1 << 18)
-#  define RX_MII_ERROR		(1 << 19)
-#  define RX_DRIBBLING		(1 << 20)
-#  define RX_CRC_ERROR		(1 << 21)
-#  define RX_VLAN1		(1 << 22)
-#  define RX_VLAN2		(1 << 23)
-#  define RX_LEN_ERROR		(1 << 24)
-#  define RX_CNTRL_FRAME	(1 << 25)
-#  define RX_U_CNTRL_FRAME	(1 << 26)
-#  define RX_MCAST_FRAME	(1 << 27)
-#  define RX_BCAST_FRAME	(1 << 28)
-#  define RX_FILTER_FAIL	(1 << 29)
-#  define RX_PACKET_FILTER	(1 << 30)
-#  define RX_MISSED_FRAME	(1 << 31)
-
-#  define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
-		    RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
-		    RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
-#define MAC_RX_BUFF0_ADDR	0x4
-#  define RX_DMA_ENABLE 	(1 << 0)
-#  define RX_T_DONE		(1 << 1)
-#  define RX_GET_DMA_BUFFER(X)	(((X) >> 2) & 0x3)
-#  define RX_SET_BUFF_ADDR(X)	((X) & 0xffffffc0)
-#define MAC_RX_BUFF1_STATUS	0x10
-#define MAC_RX_BUFF1_ADDR	0x14
-#define MAC_RX_BUFF2_STATUS	0x20
-#define MAC_RX_BUFF2_ADDR	0x24
-#define MAC_RX_BUFF3_STATUS	0x30
-#define MAC_RX_BUFF3_ADDR	0x34
-
-/* UARTS 0-3 */
-#define UART_BASE		UART0_ADDR
-#ifdef	CONFIG_SOC_AU1200
-#define UART_DEBUG_BASE 	UART1_ADDR
-#else
-#define UART_DEBUG_BASE 	UART3_ADDR
-#endif
-
-#define UART_RX		0	/* Receive buffer */
-#define UART_TX		4	/* Transmit buffer */
-#define UART_IER	8	/* Interrupt Enable Register */
-#define UART_IIR	0xC	/* Interrupt ID Register */
-#define UART_FCR	0x10	/* FIFO Control Register */
-#define UART_LCR	0x14	/* Line Control Register */
-#define UART_MCR	0x18	/* Modem Control Register */
-#define UART_LSR	0x1C	/* Line Status Register */
-#define UART_MSR	0x20	/* Modem Status Register */
-#define UART_CLK	0x28	/* Baud Rate Clock Divider */
-#define UART_MOD_CNTRL	0x100	/* Module Control */
-
-#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
-#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK	0xF0 /* Mask for the FIFO trigger range */
-#define UART_FCR_R_TRIGGER_1	0x00 /* Mask for receive trigger set at 1 */
-#define UART_FCR_R_TRIGGER_4	0x40 /* Mask for receive trigger set at 4 */
-#define UART_FCR_R_TRIGGER_8	0x80 /* Mask for receive trigger set at 8 */
-#define UART_FCR_R_TRIGGER_14   0xA0 /* Mask for receive trigger set at 14 */
-#define UART_FCR_T_TRIGGER_0	0x00 /* Mask for transmit trigger set at 0 */
-#define UART_FCR_T_TRIGGER_4	0x10 /* Mask for transmit trigger set at 4 */
-#define UART_FCR_T_TRIGGER_8    0x20 /* Mask for transmit trigger set at 8 */
-#define UART_FCR_T_TRIGGER_12	0x30 /* Mask for transmit trigger set at 12 */
-
-/*
- * These are the definitions for the Line Control Register
- */
-#define UART_LCR_SBC	0x40	/* Set break control */
-#define UART_LCR_SPAR	0x20	/* Stick parity (?) */
-#define UART_LCR_EPAR	0x10	/* Even parity select */
-#define UART_LCR_PARITY	0x08	/* Parity Enable */
-#define UART_LCR_STOP	0x04	/* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5  0x00	/* Wordlength: 5 bits */
-#define UART_LCR_WLEN6  0x01	/* Wordlength: 6 bits */
-#define UART_LCR_WLEN7  0x02	/* Wordlength: 7 bits */
-#define UART_LCR_WLEN8  0x03	/* Wordlength: 8 bits */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_TEMT	0x40	/* Transmitter empty */
-#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
-#define UART_LSR_BI	0x10	/* Break interrupt indicator */
-#define UART_LSR_FE	0x08	/* Frame error indicator */
-#define UART_LSR_PE	0x04	/* Parity error indicator */
-#define UART_LSR_OE	0x02	/* Overrun error indicator */
-#define UART_LSR_DR	0x01	/* Receiver data ready */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
-#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
-#define UART_IIR_MSI	0x00	/* Modem status interrupt */
-#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
-#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
-#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
-#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
-#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
-#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
-#define UART_MCR_OUT2	0x08	/* Out2 complement */
-#define UART_MCR_OUT1	0x04	/* Out1 complement */
-#define UART_MCR_RTS	0x02	/* RTS complement */
-#define UART_MCR_DTR	0x01	/* DTR complement */
-
-/*
- * These are the definitions for the Modem Status Register
- */
-#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
-#define UART_MSR_RI	0x40	/* Ring Indicator */
-#define UART_MSR_DSR	0x20	/* Data Set Ready */
-#define UART_MSR_CTS	0x10	/* Clear to Send */
-#define UART_MSR_DDCD	0x08	/* Delta DCD */
-#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
-#define UART_MSR_DDSR	0x02	/* Delta DSR */
-#define UART_MSR_DCTS	0x01	/* Delta CTS */
-#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */
-
-/* SSIO */
-#define SSI0_STATUS		0xB1600000
-#  define SSI_STATUS_BF 	(1 << 4)
-#  define SSI_STATUS_OF 	(1 << 3)
-#  define SSI_STATUS_UF 	(1 << 2)
-#  define SSI_STATUS_D		(1 << 1)
-#  define SSI_STATUS_B		(1 << 0)
-#define SSI0_INT		0xB1600004
-#  define SSI_INT_OI		(1 << 3)
-#  define SSI_INT_UI		(1 << 2)
-#  define SSI_INT_DI		(1 << 1)
-#define SSI0_INT_ENABLE 	0xB1600008
-#  define SSI_INTE_OIE		(1 << 3)
-#  define SSI_INTE_UIE		(1 << 2)
-#  define SSI_INTE_DIE		(1 << 1)
-#define SSI0_CONFIG		0xB1600020
-#  define SSI_CONFIG_AO 	(1 << 24)
-#  define SSI_CONFIG_DO 	(1 << 23)
-#  define SSI_CONFIG_ALEN_BIT	20
-#  define SSI_CONFIG_ALEN_MASK	(0x7 << 20)
-#  define SSI_CONFIG_DLEN_BIT	16
-#  define SSI_CONFIG_DLEN_MASK	(0x7 << 16)
-#  define SSI_CONFIG_DD 	(1 << 11)
-#  define SSI_CONFIG_AD 	(1 << 10)
-#  define SSI_CONFIG_BM_BIT	8
-#  define SSI_CONFIG_BM_MASK	(0x3 << 8)
-#  define SSI_CONFIG_CE 	(1 << 7)
-#  define SSI_CONFIG_DP 	(1 << 6)
-#  define SSI_CONFIG_DL 	(1 << 5)
-#  define SSI_CONFIG_EP 	(1 << 4)
-#define SSI0_ADATA		0xB1600024
-#  define SSI_AD_D		(1 << 24)
-#  define SSI_AD_ADDR_BIT	16
-#  define SSI_AD_ADDR_MASK	(0xff << 16)
-#  define SSI_AD_DATA_BIT	0
-#  define SSI_AD_DATA_MASK	(0xfff << 0)
-#define SSI0_CLKDIV		0xB1600028
-#define SSI0_CONTROL		0xB1600100
-#  define SSI_CONTROL_CD	(1 << 1)
-#  define SSI_CONTROL_E 	(1 << 0)
-
-/* SSI1 */
-#define SSI1_STATUS		0xB1680000
-#define SSI1_INT		0xB1680004
-#define SSI1_INT_ENABLE 	0xB1680008
-#define SSI1_CONFIG		0xB1680020
-#define SSI1_ADATA		0xB1680024
-#define SSI1_CLKDIV		0xB1680028
-#define SSI1_ENABLE		0xB1680100
-
-/*
- * Register content definitions
- */
-#define SSI_STATUS_BF		(1 << 4)
-#define SSI_STATUS_OF		(1 << 3)
-#define SSI_STATUS_UF		(1 << 2)
-#define SSI_STATUS_D		(1 << 1)
-#define SSI_STATUS_B		(1 << 0)
-
-/* SSI_INT */
-#define SSI_INT_OI		(1 << 3)
-#define SSI_INT_UI		(1 << 2)
-#define SSI_INT_DI		(1 << 1)
-
-/* SSI_INTEN */
-#define SSI_INTEN_OIE		(1 << 3)
-#define SSI_INTEN_UIE		(1 << 2)
-#define SSI_INTEN_DIE		(1 << 1)
-
-#define SSI_CONFIG_AO		(1 << 24)
-#define SSI_CONFIG_DO		(1 << 23)
-#define SSI_CONFIG_ALEN 	(7 << 20)
-#define SSI_CONFIG_DLEN 	(15 << 16)
-#define SSI_CONFIG_DD		(1 << 11)
-#define SSI_CONFIG_AD		(1 << 10)
-#define SSI_CONFIG_BM		(3 << 8)
-#define SSI_CONFIG_CE		(1 << 7)
-#define SSI_CONFIG_DP		(1 << 6)
-#define SSI_CONFIG_DL		(1 << 5)
-#define SSI_CONFIG_EP		(1 << 4)
-#define SSI_CONFIG_ALEN_N(N)	((N-1) << 20)
-#define SSI_CONFIG_DLEN_N(N)	((N-1) << 16)
-#define SSI_CONFIG_BM_HI	(0 << 8)
-#define SSI_CONFIG_BM_LO	(1 << 8)
-#define SSI_CONFIG_BM_CY	(2 << 8)
-
-#define SSI_ADATA_D		(1 << 24)
-#define SSI_ADATA_ADDR		(0xFF << 16)
-#define SSI_ADATA_DATA		0x0FFF
-#define SSI_ADATA_ADDR_N(N)	(N << 16)
-
-#define SSI_ENABLE_CD		(1 << 1)
-#define SSI_ENABLE_E		(1 << 0)
-
-/* IrDA Controller */
-#define IRDA_BASE		0xB0300000
-#define IR_RING_PTR_STATUS	(IRDA_BASE + 0x00)
-#define IR_RING_BASE_ADDR_H	(IRDA_BASE + 0x04)
-#define IR_RING_BASE_ADDR_L	(IRDA_BASE + 0x08)
-#define IR_RING_SIZE		(IRDA_BASE + 0x0C)
-#define IR_RING_PROMPT		(IRDA_BASE + 0x10)
-#define IR_RING_ADDR_CMPR	(IRDA_BASE + 0x14)
-#define IR_INT_CLEAR		(IRDA_BASE + 0x18)
-#define IR_CONFIG_1		(IRDA_BASE + 0x20)
-#  define IR_RX_INVERT_LED	(1 << 0)
-#  define IR_TX_INVERT_LED	(1 << 1)
-#  define IR_ST 		(1 << 2)
-#  define IR_SF 		(1 << 3)
-#  define IR_SIR		(1 << 4)
-#  define IR_MIR		(1 << 5)
-#  define IR_FIR		(1 << 6)
-#  define IR_16CRC		(1 << 7)
-#  define IR_TD 		(1 << 8)
-#  define IR_RX_ALL		(1 << 9)
-#  define IR_DMA_ENABLE 	(1 << 10)
-#  define IR_RX_ENABLE		(1 << 11)
-#  define IR_TX_ENABLE		(1 << 12)
-#  define IR_LOOPBACK		(1 << 14)
-#  define IR_SIR_MODE		(IR_SIR | IR_DMA_ENABLE | \
-				 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
-#define IR_SIR_FLAGS		(IRDA_BASE + 0x24)
-#define IR_ENABLE		(IRDA_BASE + 0x28)
-#  define IR_RX_STATUS		(1 << 9)
-#  define IR_TX_STATUS		(1 << 10)
-#define IR_READ_PHY_CONFIG	(IRDA_BASE + 0x2C)
-#define IR_WRITE_PHY_CONFIG	(IRDA_BASE + 0x30)
-#define IR_MAX_PKT_LEN		(IRDA_BASE + 0x34)
-#define IR_RX_BYTE_CNT		(IRDA_BASE + 0x38)
-#define IR_CONFIG_2		(IRDA_BASE + 0x3C)
-#  define IR_MODE_INV		(1 << 0)
-#  define IR_ONE_PIN		(1 << 1)
-#define IR_INTERFACE_CONFIG	(IRDA_BASE + 0x40)
-
-/* GPIO */
-#define SYS_PINFUNC		0xB190002C
-#  define SYS_PF_USB		(1 << 15)	/* 2nd USB device/host */
-#  define SYS_PF_U3		(1 << 14)	/* GPIO23/U3TXD */
-#  define SYS_PF_U2		(1 << 13)	/* GPIO22/U2TXD */
-#  define SYS_PF_U1		(1 << 12)	/* GPIO21/U1TXD */
-#  define SYS_PF_SRC		(1 << 11)	/* GPIO6/SROMCKE */
-#  define SYS_PF_CK5		(1 << 10)	/* GPIO3/CLK5 */
-#  define SYS_PF_CK4		(1 << 9)	/* GPIO2/CLK4 */
-#  define SYS_PF_IRF		(1 << 8)	/* GPIO15/IRFIRSEL */
-#  define SYS_PF_UR3		(1 << 7)	/* GPIO[14:9]/UART3 */
-#  define SYS_PF_I2D		(1 << 6)	/* GPIO8/I2SDI */
-#  define SYS_PF_I2S		(1 << 5)	/* I2S/GPIO[29:31] */
-#  define SYS_PF_NI2		(1 << 4)	/* NI2/GPIO[24:28] */
-#  define SYS_PF_U0		(1 << 3)	/* U0TXD/GPIO20 */
-#  define SYS_PF_RD		(1 << 2)	/* IRTXD/GPIO19 */
-#  define SYS_PF_A97		(1 << 1)	/* AC97/SSL1 */
-#  define SYS_PF_S0		(1 << 0)	/* SSI_0/GPIO[16:18] */
-
-/* Au1100 only */
-#  define SYS_PF_PC		(1 << 18)	/* PCMCIA/GPIO[207:204] */
-#  define SYS_PF_LCD		(1 << 17)	/* extern lcd/GPIO[203:200] */
-#  define SYS_PF_CS		(1 << 16)	/* EXTCLK0/32KHz to gpio2 */
-#  define SYS_PF_EX0		(1 << 9)	/* GPIO2/clock */
-
-/* Au1550 only.  Redefines lots of pins */
-#  define SYS_PF_PSC2_MASK	(7 << 17)
-#  define SYS_PF_PSC2_AC97	0
-#  define SYS_PF_PSC2_SPI	0
-#  define SYS_PF_PSC2_I2S	(1 << 17)
-#  define SYS_PF_PSC2_SMBUS	(3 << 17)
-#  define SYS_PF_PSC2_GPIO	(7 << 17)
-#  define SYS_PF_PSC3_MASK	(7 << 20)
-#  define SYS_PF_PSC3_AC97	0
-#  define SYS_PF_PSC3_SPI	0
-#  define SYS_PF_PSC3_I2S	(1 << 20)
-#  define SYS_PF_PSC3_SMBUS	(3 << 20)
-#  define SYS_PF_PSC3_GPIO	(7 << 20)
-#  define SYS_PF_PSC1_S1	(1 << 1)
-#  define SYS_PF_MUST_BE_SET	((1 << 5) | (1 << 2))
-
-/* Au1200 only */
-#ifdef CONFIG_SOC_AU1200
-#define SYS_PINFUNC_DMA 	(1 << 31)
-#define SYS_PINFUNC_S0A 	(1 << 30)
-#define SYS_PINFUNC_S1A 	(1 << 29)
-#define SYS_PINFUNC_LP0 	(1 << 28)
-#define SYS_PINFUNC_LP1 	(1 << 27)
-#define SYS_PINFUNC_LD16 	(1 << 26)
-#define SYS_PINFUNC_LD8 	(1 << 25)
-#define SYS_PINFUNC_LD1 	(1 << 24)
-#define SYS_PINFUNC_LD0 	(1 << 23)
-#define SYS_PINFUNC_P1A 	(3 << 21)
-#define SYS_PINFUNC_P1B 	(1 << 20)
-#define SYS_PINFUNC_FS3 	(1 << 19)
-#define SYS_PINFUNC_P0A 	(3 << 17)
-#define SYS_PINFUNC_CS		(1 << 16)
-#define SYS_PINFUNC_CIM 	(1 << 15)
-#define SYS_PINFUNC_P1C 	(1 << 14)
-#define SYS_PINFUNC_U1T 	(1 << 12)
-#define SYS_PINFUNC_U1R 	(1 << 11)
-#define SYS_PINFUNC_EX1 	(1 << 10)
-#define SYS_PINFUNC_EX0 	(1 << 9)
-#define SYS_PINFUNC_U0R 	(1 << 8)
-#define SYS_PINFUNC_MC		(1 << 7)
-#define SYS_PINFUNC_S0B 	(1 << 6)
-#define SYS_PINFUNC_S0C 	(1 << 5)
-#define SYS_PINFUNC_P0B 	(1 << 4)
-#define SYS_PINFUNC_U0T 	(1 << 3)
-#define SYS_PINFUNC_S1B 	(1 << 2)
-#endif
-
-#define SYS_TRIOUTRD		0xB1900100
-#define SYS_TRIOUTCLR		0xB1900100
-#define SYS_OUTPUTRD		0xB1900108
-#define SYS_OUTPUTSET		0xB1900108
-#define SYS_OUTPUTCLR		0xB190010C
-#define SYS_PINSTATERD		0xB1900110
-#define SYS_PININPUTEN		0xB1900110
-
-/* GPIO2, Au1500, Au1550 only */
-#define GPIO2_BASE		0xB1700000
-#define GPIO2_DIR		(GPIO2_BASE + 0)
-#define GPIO2_OUTPUT		(GPIO2_BASE + 8)
-#define GPIO2_PINSTATE		(GPIO2_BASE + 0xC)
-#define GPIO2_INTENABLE 	(GPIO2_BASE + 0x10)
-#define GPIO2_ENABLE		(GPIO2_BASE + 0x14)
-
-/* Power Management */
-#define SYS_SCRATCH0		0xB1900018
-#define SYS_SCRATCH1		0xB190001C
-#define SYS_WAKEMSK		0xB1900034
-#define SYS_ENDIAN		0xB1900038
-#define SYS_POWERCTRL		0xB190003C
-#define SYS_WAKESRC		0xB190005C
-#define SYS_SLPPWR		0xB1900078
-#define SYS_SLEEP		0xB190007C
-
-/* Clock Controller */
-#define SYS_FREQCTRL0		0xB1900020
-#  define SYS_FC_FRDIV2_BIT	22
-#  define SYS_FC_FRDIV2_MASK	(0xff << SYS_FC_FRDIV2_BIT)
-#  define SYS_FC_FE2		(1 << 21)
-#  define SYS_FC_FS2		(1 << 20)
-#  define SYS_FC_FRDIV1_BIT	12
-#  define SYS_FC_FRDIV1_MASK	(0xff << SYS_FC_FRDIV1_BIT)
-#  define SYS_FC_FE1		(1 << 11)
-#  define SYS_FC_FS1		(1 << 10)
-#  define SYS_FC_FRDIV0_BIT	2
-#  define SYS_FC_FRDIV0_MASK	(0xff << SYS_FC_FRDIV0_BIT)
-#  define SYS_FC_FE0		(1 << 1)
-#  define SYS_FC_FS0		(1 << 0)
-#define SYS_FREQCTRL1		0xB1900024
-#  define SYS_FC_FRDIV5_BIT	22
-#  define SYS_FC_FRDIV5_MASK	(0xff << SYS_FC_FRDIV5_BIT)
-#  define SYS_FC_FE5		(1 << 21)
-#  define SYS_FC_FS5		(1 << 20)
-#  define SYS_FC_FRDIV4_BIT	12
-#  define SYS_FC_FRDIV4_MASK	(0xff << SYS_FC_FRDIV4_BIT)
-#  define SYS_FC_FE4		(1 << 11)
-#  define SYS_FC_FS4		(1 << 10)
-#  define SYS_FC_FRDIV3_BIT	2
-#  define SYS_FC_FRDIV3_MASK	(0xff << SYS_FC_FRDIV3_BIT)
-#  define SYS_FC_FE3		(1 << 1)
-#  define SYS_FC_FS3		(1 << 0)
-#define SYS_CLKSRC		0xB1900028
-#  define SYS_CS_ME1_BIT	27
-#  define SYS_CS_ME1_MASK	(0x7 << SYS_CS_ME1_BIT)
-#  define SYS_CS_DE1		(1 << 26)
-#  define SYS_CS_CE1		(1 << 25)
-#  define SYS_CS_ME0_BIT	22
-#  define SYS_CS_ME0_MASK	(0x7 << SYS_CS_ME0_BIT)
-#  define SYS_CS_DE0		(1 << 21)
-#  define SYS_CS_CE0		(1 << 20)
-#  define SYS_CS_MI2_BIT	17
-#  define SYS_CS_MI2_MASK	(0x7 << SYS_CS_MI2_BIT)
-#  define SYS_CS_DI2		(1 << 16)
-#  define SYS_CS_CI2		(1 << 15)
-#ifdef CONFIG_SOC_AU1100
-#  define SYS_CS_ML_BIT 	7
-#  define SYS_CS_ML_MASK	(0x7 << SYS_CS_ML_BIT)
-#  define SYS_CS_DL		(1 << 6)
-#  define SYS_CS_CL		(1 << 5)
-#else
-#  define SYS_CS_MUH_BIT	12
-#  define SYS_CS_MUH_MASK	(0x7 << SYS_CS_MUH_BIT)
-#  define SYS_CS_DUH		(1 << 11)
-#  define SYS_CS_CUH		(1 << 10)
-#  define SYS_CS_MUD_BIT	7
-#  define SYS_CS_MUD_MASK	(0x7 << SYS_CS_MUD_BIT)
-#  define SYS_CS_DUD		(1 << 6)
-#  define SYS_CS_CUD		(1 << 5)
-#endif
-#  define SYS_CS_MIR_BIT	2
-#  define SYS_CS_MIR_MASK	(0x7 << SYS_CS_MIR_BIT)
-#  define SYS_CS_DIR		(1 << 1)
-#  define SYS_CS_CIR		(1 << 0)
-
-#  define SYS_CS_MUX_AUX	0x1
-#  define SYS_CS_MUX_FQ0	0x2
-#  define SYS_CS_MUX_FQ1	0x3
-#  define SYS_CS_MUX_FQ2	0x4
-#  define SYS_CS_MUX_FQ3	0x5
-#  define SYS_CS_MUX_FQ4	0x6
-#  define SYS_CS_MUX_FQ5	0x7
-#define SYS_CPUPLL		0xB1900060
-#define SYS_AUXPLL		0xB1900064
-
-/* AC97 Controller */
-#define AC97C_CONFIG		0xB0000000
-#  define AC97C_RECV_SLOTS_BIT	13
-#  define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
-#  define AC97C_XMIT_SLOTS_BIT	3
-#  define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
-#  define AC97C_SG		(1 << 2)
-#  define AC97C_SYNC		(1 << 1)
-#  define AC97C_RESET		(1 << 0)
-#define AC97C_STATUS		0xB0000004
-#  define AC97C_XU		(1 << 11)
-#  define AC97C_XO		(1 << 10)
-#  define AC97C_RU		(1 << 9)
-#  define AC97C_RO		(1 << 8)
-#  define AC97C_READY		(1 << 7)
-#  define AC97C_CP		(1 << 6)
-#  define AC97C_TR		(1 << 5)
-#  define AC97C_TE		(1 << 4)
-#  define AC97C_TF		(1 << 3)
-#  define AC97C_RR		(1 << 2)
-#  define AC97C_RE		(1 << 1)
-#  define AC97C_RF		(1 << 0)
-#define AC97C_DATA		0xB0000008
-#define AC97C_CMD		0xB000000C
-#  define AC97C_WD_BIT		16
-#  define AC97C_READ		(1 << 7)
-#  define AC97C_INDEX_MASK	0x7f
-#define AC97C_CNTRL		0xB0000010
-#  define AC97C_RS		(1 << 1)
-#  define AC97C_CE		(1 << 0)
-
-/* Secure Digital (SD) Controller */
-#define SD0_XMIT_FIFO	0xB0600000
-#define SD0_RECV_FIFO	0xB0600004
-#define SD1_XMIT_FIFO	0xB0680000
-#define SD1_RECV_FIFO	0xB0680004
-
-#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
-/* Au1500 PCI Controller */
-#define Au1500_CFG_BASE 	0xB4005000	/* virtual, KSEG1 addr */
-#define Au1500_PCI_CMEM 	(Au1500_CFG_BASE + 0)
-#define Au1500_PCI_CFG		(Au1500_CFG_BASE + 4)
-#  define PCI_ERROR		((1 << 22) | (1 << 23) | (1 << 24) | \
-				 (1 << 25) | (1 << 26) | (1 << 27))
-#define Au1500_PCI_B2BMASK_CCH	(Au1500_CFG_BASE + 8)
-#define Au1500_PCI_B2B0_VID	(Au1500_CFG_BASE + 0xC)
-#define Au1500_PCI_B2B1_ID	(Au1500_CFG_BASE + 0x10)
-#define Au1500_PCI_MWMASK_DEV	(Au1500_CFG_BASE + 0x14)
-#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
-#define Au1500_PCI_ERR_ADDR	(Au1500_CFG_BASE + 0x1C)
-#define Au1500_PCI_SPEC_INTACK	(Au1500_CFG_BASE + 0x20)
-#define Au1500_PCI_ID		(Au1500_CFG_BASE + 0x100)
-#define Au1500_PCI_STATCMD	(Au1500_CFG_BASE + 0x104)
-#define Au1500_PCI_CLASSREV	(Au1500_CFG_BASE + 0x108)
-#define Au1500_PCI_HDRTYPE	(Au1500_CFG_BASE + 0x10C)
-#define Au1500_PCI_MBAR 	(Au1500_CFG_BASE + 0x110)
-
-#define Au1500_PCI_HDR		0xB4005100	/* virtual, KSEG1 addr */
-
-/*
- * All of our structures, like PCI resource, have 32-bit members.
- * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
- * hard to store 0x4 0000 0000 in a 32-bit type.  We require a small patch
- * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
- * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
- * addresses.  For PCI I/O, it's simpler because we get to do the ioremap
- * ourselves and then adjust the device's resources.
- */
-#define Au1500_EXT_CFG		0x600000000ULL
-#define Au1500_EXT_CFG_TYPE1	0x680000000ULL
-#define Au1500_PCI_IO_START	0x500000000ULL
-#define Au1500_PCI_IO_END	0x5000FFFFFULL
-#define Au1500_PCI_MEM_START	0x440000000ULL
-#define Au1500_PCI_MEM_END	0x44FFFFFFFULL
-
-#define PCI_IO_START	0x00001000
-#define PCI_IO_END	0x000FFFFF
-#define PCI_MEM_START	0x40000000
-#define PCI_MEM_END	0x4FFFFFFF
-
-#define PCI_FIRST_DEVFN (0 << 3)
-#define PCI_LAST_DEVFN	(19 << 3)
-
-#define IOPORT_RESOURCE_START	0x00001000	/* skip legacy probing */
-#define IOPORT_RESOURCE_END	0xffffffff
-#define IOMEM_RESOURCE_START	0x10000000
-#define IOMEM_RESOURCE_END	0xffffffff
-
-#else /* Au1000 and Au1100 and Au1200 */
-
-/* Don't allow any legacy ports probing */
-#define IOPORT_RESOURCE_START	0x10000000
-#define IOPORT_RESOURCE_END	0xffffffff
-#define IOMEM_RESOURCE_START	0x10000000
-#define IOMEM_RESOURCE_END	0xffffffff
-
-#define PCI_IO_START	0
-#define PCI_IO_END	0
-#define PCI_MEM_START	0
-#define PCI_MEM_END	0
-#define PCI_FIRST_DEVFN 0
-#define PCI_LAST_DEVFN	0
-
-#endif
-
-#ifndef _LANGUAGE_ASSEMBLY
-typedef volatile struct {
-	/* 0x0000 */ u32 toytrim;
-	/* 0x0004 */ u32 toywrite;
-	/* 0x0008 */ u32 toymatch0;
-	/* 0x000C */ u32 toymatch1;
-	/* 0x0010 */ u32 toymatch2;
-	/* 0x0014 */ u32 cntrctrl;
-	/* 0x0018 */ u32 scratch0;
-	/* 0x001C */ u32 scratch1;
-	/* 0x0020 */ u32 freqctrl0;
-	/* 0x0024 */ u32 freqctrl1;
-	/* 0x0028 */ u32 clksrc;
-	/* 0x002C */ u32 pinfunc;
-	/* 0x0030 */ u32 reserved0;
-	/* 0x0034 */ u32 wakemsk;
-	/* 0x0038 */ u32 endian;
-	/* 0x003C */ u32 powerctrl;
-	/* 0x0040 */ u32 toyread;
-	/* 0x0044 */ u32 rtctrim;
-	/* 0x0048 */ u32 rtcwrite;
-	/* 0x004C */ u32 rtcmatch0;
-	/* 0x0050 */ u32 rtcmatch1;
-	/* 0x0054 */ u32 rtcmatch2;
-	/* 0x0058 */ u32 rtcread;
-	/* 0x005C */ u32 wakesrc;
-	/* 0x0060 */ u32 cpupll;
-	/* 0x0064 */ u32 auxpll;
-	/* 0x0068 */ u32 reserved1;
-	/* 0x006C */ u32 reserved2;
-	/* 0x0070 */ u32 reserved3;
-	/* 0x0074 */ u32 reserved4;
-	/* 0x0078 */ u32 slppwr;
-	/* 0x007C */ u32 sleep;
-	/* 0x0080 */ u32 reserved5[32];
-	/* 0x0100 */ u32 trioutrd;
-#define trioutclr trioutrd
-	/* 0x0104 */ u32 reserved6;
-	/* 0x0108 */ u32 outputrd;
-#define outputset outputrd
-	/* 0x010C */ u32 outputclr;
-	/* 0x0110 */ u32 pinstaterd;
-#define pininputen pinstaterd
-} AU1X00_SYS;
-
-static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
-
-#endif
-
-/*
- * Processor information based on PRID.
- * Copied from PowerPC.
- */
-#ifndef _LANGUAGE_ASSEMBLY
-struct cpu_spec {
-	/* CPU is matched via (PRID & prid_mask) == prid_value */
-	unsigned int	prid_mask;
-	unsigned int	prid_value;
-
-	char		*cpu_name;
-	unsigned char	cpu_od;		/* Set Config[OD] */
-	unsigned char	cpu_bclk;	/* Enable BCLK switching */
-	unsigned char	cpu_pll_wo;	/* sys_cpupll reg. write-only */
-};
-
-extern struct cpu_spec	cpu_specs[];
-extern struct cpu_spec	*cur_cpu_spec[];
-#endif
-
-#endif
diff --git a/include/asm-mips/mach-au1x00/au1000_dma.h b/include/asm-mips/mach-au1x00/au1000_dma.h
deleted file mode 100644
index c333b4e1cd4..00000000000
--- a/include/asm-mips/mach-au1x00/au1000_dma.h
+++ /dev/null
@@ -1,458 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *	Defines for using and allocating DMA channels on the Alchemy
- *      Au1x00 MIPS processors.
- *
- * Copyright 2000, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#ifndef __ASM_AU1000_DMA_H
-#define __ASM_AU1000_DMA_H
-
-#include <linux/io.h>		/* need byte IO */
-#include <linux/spinlock.h>	/* And spinlocks */
-#include <linux/delay.h>
-#include <asm/system.h>
-
-#define NUM_AU1000_DMA_CHANNELS	8
-
-/* DMA Channel Base Addresses */
-#define DMA_CHANNEL_BASE	0xB4002000
-#define DMA_CHANNEL_LEN		0x00000100
-
-/* DMA Channel Register Offsets */
-#define DMA_MODE_SET		0x00000000
-#define DMA_MODE_READ		DMA_MODE_SET
-#define DMA_MODE_CLEAR		0x00000004
-/* DMA Mode register bits follow */
-#define DMA_DAH_MASK		(0x0f << 20)
-#define DMA_DID_BIT		16
-#define DMA_DID_MASK		(0x0f << DMA_DID_BIT)
-#define DMA_DS			(1 << 15)
-#define DMA_BE			(1 << 13)
-#define DMA_DR			(1 << 12)
-#define DMA_TS8 		(1 << 11)
-#define DMA_DW_BIT		9
-#define DMA_DW_MASK		(0x03 << DMA_DW_BIT)
-#define DMA_DW8			(0 << DMA_DW_BIT)
-#define DMA_DW16		(1 << DMA_DW_BIT)
-#define DMA_DW32		(2 << DMA_DW_BIT)
-#define DMA_NC			(1 << 8)
-#define DMA_IE			(1 << 7)
-#define DMA_HALT		(1 << 6)
-#define DMA_GO			(1 << 5)
-#define DMA_AB			(1 << 4)
-#define DMA_D1			(1 << 3)
-#define DMA_BE1 		(1 << 2)
-#define DMA_D0			(1 << 1)
-#define DMA_BE0 		(1 << 0)
-
-#define DMA_PERIPHERAL_ADDR	0x00000008
-#define DMA_BUFFER0_START	0x0000000C
-#define DMA_BUFFER1_START	0x00000014
-#define DMA_BUFFER0_COUNT	0x00000010
-#define DMA_BUFFER1_COUNT	0x00000018
-#define DMA_BAH_BIT	16
-#define DMA_BAH_MASK	(0x0f << DMA_BAH_BIT)
-#define DMA_COUNT_BIT	0
-#define DMA_COUNT_MASK	(0xffff << DMA_COUNT_BIT)
-
-/* DMA Device IDs follow */
-enum {
-	DMA_ID_UART0_TX = 0,
-	DMA_ID_UART0_RX,
-	DMA_ID_GP04,
-	DMA_ID_GP05,
-	DMA_ID_AC97C_TX,
-	DMA_ID_AC97C_RX,
-	DMA_ID_UART3_TX,
-	DMA_ID_UART3_RX,
-	DMA_ID_USBDEV_EP0_RX,
-	DMA_ID_USBDEV_EP0_TX,
-	DMA_ID_USBDEV_EP2_TX,
-	DMA_ID_USBDEV_EP3_TX,
-	DMA_ID_USBDEV_EP4_RX,
-	DMA_ID_USBDEV_EP5_RX,
-	DMA_ID_I2S_TX,
-	DMA_ID_I2S_RX,
-	DMA_NUM_DEV
-};
-
-/* DMA Device ID's for 2nd bank (AU1100) follow */
-enum {
-	DMA_ID_SD0_TX = 0,
-	DMA_ID_SD0_RX,
-	DMA_ID_SD1_TX,
-	DMA_ID_SD1_RX,
-	DMA_NUM_DEV_BANK2
-};
-
-struct dma_chan {
-	int dev_id;		/* this channel is allocated if >= 0, */
-				/* free otherwise */
-	unsigned int io;
-	const char *dev_str;
-	int irq;
-	void *irq_dev;
-	unsigned int fifo_addr;
-	unsigned int mode;
-};
-
-/* These are in arch/mips/au1000/common/dma.c */
-extern struct dma_chan au1000_dma_table[];
-extern int request_au1000_dma(int dev_id,
-			      const char *dev_str,
-			      irq_handler_t irqhandler,
-			      unsigned long irqflags,
-			      void *irq_dev_id);
-extern void free_au1000_dma(unsigned int dmanr);
-extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
-				int length, int *eof, void *data);
-extern void dump_au1000_dma_channel(unsigned int dmanr);
-extern spinlock_t au1000_dma_spin_lock;
-
-static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
-{
-	if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
-	    au1000_dma_table[dmanr].dev_id < 0)
-		return NULL;
-	return &au1000_dma_table[dmanr];
-}
-
-static inline unsigned long claim_dma_lock(void)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&au1000_dma_spin_lock, flags);
-	return flags;
-}
-
-static inline void release_dma_lock(unsigned long flags)
-{
-	spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
-}
-
-/*
- * Set the DMA buffer enable bits in the mode register.
- */
-static inline void enable_dma_buffer0(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
-}
-
-static inline void enable_dma_buffer1(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
-}
-static inline void enable_dma_buffers(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
-}
-
-static inline void start_dma(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	au_writel(DMA_GO, chan->io + DMA_MODE_SET);
-}
-
-#define DMA_HALT_POLL 0x5000
-
-static inline void halt_dma(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-	int i;
-
-	if (!chan)
-		return;
-	au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
-
-	/* Poll the halt bit */
-	for (i = 0; i < DMA_HALT_POLL; i++)
-		if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
-			break;
-	if (i == DMA_HALT_POLL)
-		printk(KERN_INFO "halt_dma: HALT poll expired!\n");
-}
-
-static inline void disable_dma(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-
-	halt_dma(dmanr);
-
-	/* Now we can disable the buffers */
-	au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
-}
-
-static inline int dma_halted(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return 1;
-	return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
-}
-
-/* Initialize a DMA channel. */
-static inline void init_dma(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-	u32 mode;
-
-	if (!chan)
-		return;
-
-	disable_dma(dmanr);
-
-	/* Set device FIFO address */
-	au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
-
-	mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
-	if (chan->irq)
-		mode |= DMA_IE;
-
-	au_writel(~mode, chan->io + DMA_MODE_CLEAR);
-	au_writel(mode,  chan->io + DMA_MODE_SET);
-}
-
-/*
- * Set mode for a specific DMA channel
- */
-static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	/*
-	 * set_dma_mode is only allowed to change endianess, direction,
-	 * transfer size, device FIFO width, and coherency settings.
-	 * Make sure anything else is masked off.
-	 */
-	mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
-	chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
-	chan->mode |= mode;
-}
-
-static inline unsigned int get_dma_mode(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return 0;
-	return chan->mode;
-}
-
-static inline int get_dma_active_buffer(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return -1;
-	return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
-}
-
-/*
- * Set the device FIFO address for a specific DMA channel - only
- * applicable to GPO4 and GPO5. All the other devices have fixed
- * FIFO addresses.
- */
-static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-
-	if (chan->mode & DMA_DS)	/* second bank of device IDs */
-		return;
-
-	if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
-		return;
-
-	au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
-}
-
-/*
- * Clear the DMA buffer done bits in the mode register.
- */
-static inline void clear_dma_done0(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
-}
-
-static inline void clear_dma_done1(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
-}
-
-/*
- * This does nothing - not applicable to Au1000 DMA.
- */
-static inline void set_dma_page(unsigned int dmanr, char pagenr)
-{
-}
-
-/*
- * Set Buffer 0 transfer address for specific DMA channel.
- */
-static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	au_writel(a, chan->io + DMA_BUFFER0_START);
-}
-
-/*
- * Set Buffer 1 transfer address for specific DMA channel.
- */
-static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	au_writel(a, chan->io + DMA_BUFFER1_START);
-}
-
-
-/*
- * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
- */
-static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	count &= DMA_COUNT_MASK;
-	au_writel(count, chan->io + DMA_BUFFER0_COUNT);
-}
-
-/*
- * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
- */
-static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	count &= DMA_COUNT_MASK;
-	au_writel(count, chan->io + DMA_BUFFER1_COUNT);
-}
-
-/*
- * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
- */
-static inline void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return;
-	count &= DMA_COUNT_MASK;
-	au_writel(count, chan->io + DMA_BUFFER0_COUNT);
-	au_writel(count, chan->io + DMA_BUFFER1_COUNT);
-}
-
-/*
- * Returns which buffer has its done bit set in the mode register.
- * Returns -1 if neither or both done bits set.
- */
-static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return 0;
-	return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
-}
-
-
-/*
- * Returns the DMA channel's Buffer Done IRQ number.
- */
-static inline int get_dma_done_irq(unsigned int dmanr)
-{
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return -1;
-	return chan->irq;
-}
-
-/*
- * Get DMA residue count. Returns the number of _bytes_ left to transfer.
- */
-static inline int get_dma_residue(unsigned int dmanr)
-{
-	int curBufCntReg, count;
-	struct dma_chan *chan = get_dma_chan(dmanr);
-
-	if (!chan)
-		return 0;
-
-	curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
-	    DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
-
-	count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
-
-	if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
-		count <<= 1;
-	else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
-		count <<= 2;
-
-	return count;
-}
-
-#endif /* __ASM_AU1000_DMA_H */
diff --git a/include/asm-mips/mach-au1x00/au1000_gpio.h b/include/asm-mips/mach-au1x00/au1000_gpio.h
deleted file mode 100644
index d8c96fda554..00000000000
--- a/include/asm-mips/mach-au1x00/au1000_gpio.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * FILE NAME au1000_gpio.h
- *
- * BRIEF MODULE DESCRIPTION
- *	API to Alchemy Au1xx0 GPIO device.
- *
- *  Author: MontaVista Software, Inc.  <source@mvista.com>
- *          Steve Longerbeam
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __AU1000_GPIO_H
-#define __AU1000_GPIO_H
-
-#include <linux/ioctl.h>
-
-#define AU1000GPIO_IOC_MAGIC 'A'
-
-#define AU1000GPIO_IN		_IOR(AU1000GPIO_IOC_MAGIC, 0, int)
-#define AU1000GPIO_SET		_IOW(AU1000GPIO_IOC_MAGIC, 1, int)
-#define AU1000GPIO_CLEAR	_IOW(AU1000GPIO_IOC_MAGIC, 2, int)
-#define AU1000GPIO_OUT		_IOW(AU1000GPIO_IOC_MAGIC, 3, int)
-#define AU1000GPIO_TRISTATE	_IOW(AU1000GPIO_IOC_MAGIC, 4, int)
-#define AU1000GPIO_AVAIL_MASK	_IOR(AU1000GPIO_IOC_MAGIC, 5, int)
-
-#ifdef __KERNEL__
-extern u32 get_au1000_avail_gpio_mask(void);
-extern int au1000gpio_tristate(u32 data);
-extern int au1000gpio_in(u32 *data);
-extern int au1000gpio_set(u32 data);
-extern int au1000gpio_clear(u32 data);
-extern int au1000gpio_out(u32 data);
-#endif
-
-#endif
diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h
deleted file mode 100644
index c35e2091849..00000000000
--- a/include/asm-mips/mach-au1x00/au1100_mmc.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *	Defines for using the MMC/SD controllers on the
- *      Alchemy Au1100 mips processor.
- *
- * Copyright (c) 2003 Embedded Edge, LLC.
- * Author: Embedded Edge, LLC.
- *         	dan@embeddededge.com or tim@embeddededge.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-/*
- * AU1100 MMC/SD definitions.
- *
- * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary"
- *    June, 2003
- */
-
-#ifndef __ASM_AU1100_MMC_H
-#define __ASM_AU1100_MMC_H
-
-#include <linux/leds.h>
-
-struct au1xmmc_platform_data {
-	int(*cd_setup)(void *mmc_host, int on);
-	int(*card_inserted)(void *mmc_host);
-	int(*card_readonly)(void *mmc_host);
-	void(*set_power)(void *mmc_host, int state);
-	struct led_classdev *led;
-};
-
-#define SD0_BASE	0xB0600000
-#define SD1_BASE	0xB0680000
-
-
-/*
- *  Register offsets.
- */
-#define SD_TXPORT	(0x0000)
-#define SD_RXPORT	(0x0004)
-#define SD_CONFIG	(0x0008)
-#define SD_ENABLE	(0x000C)
-#define SD_CONFIG2	(0x0010)
-#define SD_BLKSIZE	(0x0014)
-#define SD_STATUS	(0x0018)
-#define SD_DEBUG	(0x001C)
-#define SD_CMD		(0x0020)
-#define SD_CMDARG	(0x0024)
-#define SD_RESP3	(0x0028)
-#define SD_RESP2	(0x002C)
-#define SD_RESP1	(0x0030)
-#define SD_RESP0	(0x0034)
-#define SD_TIMEOUT	(0x0038)
-
-
-/*
- *  SD_TXPORT bit definitions.
- */
-#define SD_TXPORT_TXD	(0x000000ff)
-
-
-/*
- *  SD_RXPORT bit definitions.
- */
-#define SD_RXPORT_RXD	(0x000000ff)
-
-
-/*
- *  SD_CONFIG bit definitions.
- */
-#define SD_CONFIG_DIV	(0x000001ff)
-#define SD_CONFIG_DE	(0x00000200)
-#define SD_CONFIG_NE	(0x00000400)
-#define SD_CONFIG_TU	(0x00000800)
-#define SD_CONFIG_TO	(0x00001000)
-#define SD_CONFIG_RU	(0x00002000)
-#define SD_CONFIG_RO	(0x00004000)
-#define SD_CONFIG_I	(0x00008000)
-#define SD_CONFIG_CR	(0x00010000)
-#define SD_CONFIG_RAT	(0x00020000)
-#define SD_CONFIG_DD	(0x00040000)
-#define SD_CONFIG_DT	(0x00080000)
-#define SD_CONFIG_SC	(0x00100000)
-#define SD_CONFIG_RC	(0x00200000)
-#define SD_CONFIG_WC	(0x00400000)
-#define SD_CONFIG_xxx	(0x00800000)
-#define SD_CONFIG_TH	(0x01000000)
-#define SD_CONFIG_TE	(0x02000000)
-#define SD_CONFIG_TA	(0x04000000)
-#define SD_CONFIG_RH	(0x08000000)
-#define SD_CONFIG_RA	(0x10000000)
-#define SD_CONFIG_RF	(0x20000000)
-#define SD_CONFIG_CD	(0x40000000)
-#define SD_CONFIG_SI	(0x80000000)
-
-
-/*
- *  SD_ENABLE bit definitions.
- */
-#define SD_ENABLE_CE	(0x00000001)
-#define SD_ENABLE_R	(0x00000002)
-
-
-/*
- *  SD_CONFIG2 bit definitions.
- */
-#define SD_CONFIG2_EN	(0x00000001)
-#define SD_CONFIG2_FF	(0x00000002)
-#define SD_CONFIG2_xx1	(0x00000004)
-#define SD_CONFIG2_DF	(0x00000008)
-#define SD_CONFIG2_DC	(0x00000010)
-#define SD_CONFIG2_xx2	(0x000000e0)
-#define SD_CONFIG2_WB	(0x00000100)
-#define SD_CONFIG2_RW	(0x00000200)
-
-
-/*
- *  SD_BLKSIZE bit definitions.
- */
-#define SD_BLKSIZE_BS	(0x000007ff)
-#define SD_BLKSIZE_BS_SHIFT	 (0)
-#define SD_BLKSIZE_BC	(0x01ff0000)
-#define SD_BLKSIZE_BC_SHIFT	(16)
-
-
-/*
- *  SD_STATUS bit definitions.
- */
-#define SD_STATUS_DCRCW	(0x00000007)
-#define SD_STATUS_xx1	(0x00000008)
-#define SD_STATUS_CB	(0x00000010)
-#define SD_STATUS_DB	(0x00000020)
-#define SD_STATUS_CF	(0x00000040)
-#define SD_STATUS_D3	(0x00000080)
-#define SD_STATUS_xx2	(0x00000300)
-#define SD_STATUS_NE	(0x00000400)
-#define SD_STATUS_TU	(0x00000800)
-#define SD_STATUS_TO	(0x00001000)
-#define SD_STATUS_RU	(0x00002000)
-#define SD_STATUS_RO	(0x00004000)
-#define SD_STATUS_I	(0x00008000)
-#define SD_STATUS_CR	(0x00010000)
-#define SD_STATUS_RAT	(0x00020000)
-#define SD_STATUS_DD	(0x00040000)
-#define SD_STATUS_DT	(0x00080000)
-#define SD_STATUS_SC	(0x00100000)
-#define SD_STATUS_RC	(0x00200000)
-#define SD_STATUS_WC	(0x00400000)
-#define SD_STATUS_xx3	(0x00800000)
-#define SD_STATUS_TH	(0x01000000)
-#define SD_STATUS_TE	(0x02000000)
-#define SD_STATUS_TA	(0x04000000)
-#define SD_STATUS_RH	(0x08000000)
-#define SD_STATUS_RA	(0x10000000)
-#define SD_STATUS_RF	(0x20000000)
-#define SD_STATUS_CD	(0x40000000)
-#define SD_STATUS_SI	(0x80000000)
-
-
-/*
- *  SD_CMD bit definitions.
- */
-#define SD_CMD_GO	(0x00000001)
-#define SD_CMD_RY	(0x00000002)
-#define SD_CMD_xx1	(0x0000000c)
-#define SD_CMD_CT_MASK	(0x000000f0)
-#define SD_CMD_CT_0	(0x00000000)
-#define SD_CMD_CT_1	(0x00000010)
-#define SD_CMD_CT_2	(0x00000020)
-#define SD_CMD_CT_3	(0x00000030)
-#define SD_CMD_CT_4	(0x00000040)
-#define SD_CMD_CT_5	(0x00000050)
-#define SD_CMD_CT_6	(0x00000060)
-#define SD_CMD_CT_7	(0x00000070)
-#define SD_CMD_CI	(0x0000ff00)
-#define SD_CMD_CI_SHIFT		(8)
-#define SD_CMD_RT_MASK	(0x00ff0000)
-#define SD_CMD_RT_0	(0x00000000)
-#define SD_CMD_RT_1	(0x00010000)
-#define SD_CMD_RT_2	(0x00020000)
-#define SD_CMD_RT_3	(0x00030000)
-#define SD_CMD_RT_4	(0x00040000)
-#define SD_CMD_RT_5	(0x00050000)
-#define SD_CMD_RT_6	(0x00060000)
-#define SD_CMD_RT_1B	(0x00810000)
-
-
-#endif /* __ASM_AU1100_MMC_H */
-
diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/include/asm-mips/mach-au1x00/au1550_spi.h
deleted file mode 100644
index 08e1958e941..00000000000
--- a/include/asm-mips/mach-au1x00/au1550_spi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
- */
-
-#ifndef _AU1550_SPI_H_
-#define _AU1550_SPI_H_
-
-struct au1550_spi_info {
-	u32 mainclk_hz;		/* main input clock frequency of PSC */
-	u16 num_chipselect;	/* number of chipselects supported */
-	void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
-	void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
-};
-
-#endif
diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h
deleted file mode 100644
index 1b3655090ed..00000000000
--- a/include/asm-mips/mach-au1x00/au1xxx.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _AU1XXX_H_
-#define _AU1XXX_H_
-
-#include <asm/mach-au1x00/au1000.h>
-
-#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
-    defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
-#include <asm/mach-db1x00/db1x00.h>
-
-#elif defined(CONFIG_MIPS_PB1550)
-#include <asm/mach-pb1x00/pb1550.h>
-
-#elif defined(CONFIG_MIPS_PB1200)
-#include <asm/mach-pb1x00/pb1200.h>
-
-#elif defined(CONFIG_MIPS_DB1200)
-#include <asm/mach-db1x00/db1200.h>
-
-#endif
-
-#endif /* _AU1XXX_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
deleted file mode 100644
index 44a67bf05dc..00000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *	Include file for Alchemy Semiconductor's Au1550 Descriptor
- *	Based DMA Controller.
- *
- * Copyright 2004 Embedded Edge, LLC
- *	dan@embeddededge.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Specifics for the Au1xxx Descriptor-Based DMA Controller,
- * first seen in the AU1550 part.
- */
-#ifndef _AU1000_DBDMA_H_
-#define _AU1000_DBDMA_H_
-
-#ifndef _LANGUAGE_ASSEMBLY
-
-/*
- * The DMA base addresses.
- * The channels are every 256 bytes (0x0100) from the channel 0 base.
- * Interrupt status/enable is bits 15:0 for channels 15 to zero.
- */
-#define DDMA_GLOBAL_BASE	0xb4003000
-#define DDMA_CHANNEL_BASE	0xb4002000
-
-typedef volatile struct dbdma_global {
-	u32	ddma_config;
-	u32	ddma_intstat;
-	u32	ddma_throttle;
-	u32	ddma_inten;
-} dbdma_global_t;
-
-/* General Configuration. */
-#define DDMA_CONFIG_AF		(1 << 2)
-#define DDMA_CONFIG_AH		(1 << 1)
-#define DDMA_CONFIG_AL		(1 << 0)
-
-#define DDMA_THROTTLE_EN	(1 << 31)
-
-/* The structure of a DMA Channel. */
-typedef volatile struct au1xxx_dma_channel {
-	u32	ddma_cfg;	/* See below */
-	u32	ddma_desptr;	/* 32-byte aligned pointer to descriptor */
-	u32	ddma_statptr;	/* word aligned pointer to status word */
-	u32	ddma_dbell;	/* A write activates channel operation */
-	u32	ddma_irq;	/* If bit 0 set, interrupt pending */
-	u32	ddma_stat;	/* See below */
-	u32	ddma_bytecnt;	/* Byte count, valid only when chan idle */
-	/* Remainder, up to the 256 byte boundary, is reserved. */
-} au1x_dma_chan_t;
-
-#define DDMA_CFG_SED	(1 << 9)	/* source DMA level/edge detect */
-#define DDMA_CFG_SP	(1 << 8)	/* source DMA polarity */
-#define DDMA_CFG_DED	(1 << 7)	/* destination DMA level/edge detect */
-#define DDMA_CFG_DP	(1 << 6)	/* destination DMA polarity */
-#define DDMA_CFG_SYNC	(1 << 5)	/* Sync static bus controller */
-#define DDMA_CFG_PPR	(1 << 4)	/* PCI posted read/write control */
-#define DDMA_CFG_DFN	(1 << 3)	/* Descriptor fetch non-coherent */
-#define DDMA_CFG_SBE	(1 << 2)	/* Source big endian */
-#define DDMA_CFG_DBE	(1 << 1)	/* Destination big endian */
-#define DDMA_CFG_EN	(1 << 0)	/* Channel enable */
-
-/*
- * Always set when descriptor processing done, regardless of
- * interrupt enable state.  Reflected in global intstat, don't
- * clear this until global intstat is read/used.
- */
-#define DDMA_IRQ_IN	(1 << 0)
-
-#define DDMA_STAT_DB	(1 << 2)	/* Doorbell pushed */
-#define DDMA_STAT_V	(1 << 1)	/* Descriptor valid */
-#define DDMA_STAT_H	(1 << 0)	/* Channel Halted */
-
-/*
- * "Standard" DDMA Descriptor.
- * Must be 32-byte aligned.
- */
-typedef volatile struct au1xxx_ddma_desc {
-	u32	dscr_cmd0;		/* See below */
-	u32	dscr_cmd1;		/* See below */
-	u32	dscr_source0;		/* source phys address */
-	u32	dscr_source1;		/* See below */
-	u32	dscr_dest0;		/* Destination address */
-	u32	dscr_dest1;		/* See below */
-	u32	dscr_stat;		/* completion status */
-	u32	dscr_nxtptr;		/* Next descriptor pointer (mostly) */
-	/*
-	 * First 32 bytes are HW specific!!!
-	 * Lets have some SW data following -- make sure it's 32 bytes.
-	 */
-	u32	sw_status;
-	u32 	sw_context;
-	u32	sw_reserved[6];
-} au1x_ddma_desc_t;
-
-#define DSCR_CMD0_V		(1 << 31)	/* Descriptor valid */
-#define DSCR_CMD0_MEM		(1 << 30)	/* mem-mem transfer */
-#define DSCR_CMD0_SID_MASK	(0x1f << 25)	/* Source ID */
-#define DSCR_CMD0_DID_MASK	(0x1f << 20)	/* Destination ID */
-#define DSCR_CMD0_SW_MASK	(0x3 << 18)	/* Source Width */
-#define DSCR_CMD0_DW_MASK	(0x3 << 16)	/* Destination Width */
-#define DSCR_CMD0_ARB		(0x1 << 15)	/* Set for Hi Pri */
-#define DSCR_CMD0_DT_MASK	(0x3 << 13)	/* Descriptor Type */
-#define DSCR_CMD0_SN		(0x1 << 12)	/* Source non-coherent */
-#define DSCR_CMD0_DN		(0x1 << 11)	/* Destination non-coherent */
-#define DSCR_CMD0_SM		(0x1 << 10)	/* Stride mode */
-#define DSCR_CMD0_IE		(0x1 << 8)	/* Interrupt Enable */
-#define DSCR_CMD0_SP		(0x1 << 4)	/* Status pointer select */
-#define DSCR_CMD0_CV		(0x1 << 2)	/* Clear Valid when done */
-#define DSCR_CMD0_ST_MASK	(0x3 << 0)	/* Status instruction */
-
-#define SW_STATUS_INUSE 	(1 << 0)
-
-/* Command 0 device IDs. */
-#ifdef CONFIG_SOC_AU1550
-#define DSCR_CMD0_UART0_TX	0
-#define DSCR_CMD0_UART0_RX	1
-#define DSCR_CMD0_UART3_TX	2
-#define DSCR_CMD0_UART3_RX	3
-#define DSCR_CMD0_DMA_REQ0	4
-#define DSCR_CMD0_DMA_REQ1	5
-#define DSCR_CMD0_DMA_REQ2	6
-#define DSCR_CMD0_DMA_REQ3	7
-#define DSCR_CMD0_USBDEV_RX0	8
-#define DSCR_CMD0_USBDEV_TX0	9
-#define DSCR_CMD0_USBDEV_TX1	10
-#define DSCR_CMD0_USBDEV_TX2	11
-#define DSCR_CMD0_USBDEV_RX3	12
-#define DSCR_CMD0_USBDEV_RX4	13
-#define DSCR_CMD0_PSC0_TX	14
-#define DSCR_CMD0_PSC0_RX	15
-#define DSCR_CMD0_PSC1_TX	16
-#define DSCR_CMD0_PSC1_RX	17
-#define DSCR_CMD0_PSC2_TX	18
-#define DSCR_CMD0_PSC2_RX	19
-#define DSCR_CMD0_PSC3_TX	20
-#define DSCR_CMD0_PSC3_RX	21
-#define DSCR_CMD0_PCI_WRITE	22
-#define DSCR_CMD0_NAND_FLASH	23
-#define DSCR_CMD0_MAC0_RX	24
-#define DSCR_CMD0_MAC0_TX	25
-#define DSCR_CMD0_MAC1_RX	26
-#define DSCR_CMD0_MAC1_TX	27
-#endif /* CONFIG_SOC_AU1550 */
-
-#ifdef CONFIG_SOC_AU1200
-#define DSCR_CMD0_UART0_TX	0
-#define DSCR_CMD0_UART0_RX	1
-#define DSCR_CMD0_UART1_TX	2
-#define DSCR_CMD0_UART1_RX	3
-#define DSCR_CMD0_DMA_REQ0	4
-#define DSCR_CMD0_DMA_REQ1	5
-#define DSCR_CMD0_MAE_BE	6
-#define DSCR_CMD0_MAE_FE	7
-#define DSCR_CMD0_SDMS_TX0	8
-#define DSCR_CMD0_SDMS_RX0	9
-#define DSCR_CMD0_SDMS_TX1	10
-#define DSCR_CMD0_SDMS_RX1	11
-#define DSCR_CMD0_AES_TX	13
-#define DSCR_CMD0_AES_RX	12
-#define DSCR_CMD0_PSC0_TX	14
-#define DSCR_CMD0_PSC0_RX	15
-#define DSCR_CMD0_PSC1_TX	16
-#define DSCR_CMD0_PSC1_RX	17
-#define DSCR_CMD0_CIM_RXA	18
-#define DSCR_CMD0_CIM_RXB	19
-#define DSCR_CMD0_CIM_RXC	20
-#define DSCR_CMD0_MAE_BOTH	21
-#define DSCR_CMD0_LCD		22
-#define DSCR_CMD0_NAND_FLASH	23
-#define DSCR_CMD0_PSC0_SYNC	24
-#define DSCR_CMD0_PSC1_SYNC	25
-#define DSCR_CMD0_CIM_SYNC	26
-#endif /* CONFIG_SOC_AU1200 */
-
-#define DSCR_CMD0_THROTTLE	30
-#define DSCR_CMD0_ALWAYS	31
-#define DSCR_NDEV_IDS		32
-/* This macro is used to find/create custom device types */
-#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
-				  ((d) & 0xFF))
-#define DSCR_CUSTOM2DEV_ID(x)	((x) & 0xFF)
-
-#define DSCR_CMD0_SID(x)	(((x) & 0x1f) << 25)
-#define DSCR_CMD0_DID(x)	(((x) & 0x1f) << 20)
-
-/* Source/Destination transfer width. */
-#define DSCR_CMD0_BYTE		0
-#define DSCR_CMD0_HALFWORD	1
-#define DSCR_CMD0_WORD		2
-
-#define DSCR_CMD0_SW(x)		(((x) & 0x3) << 18)
-#define DSCR_CMD0_DW(x)		(((x) & 0x3) << 16)
-
-/* DDMA Descriptor Type. */
-#define DSCR_CMD0_STANDARD	0
-#define DSCR_CMD0_LITERAL	1
-#define DSCR_CMD0_CMP_BRANCH	2
-
-#define DSCR_CMD0_DT(x)		(((x) & 0x3) << 13)
-
-/* Status Instruction. */
-#define DSCR_CMD0_ST_NOCHANGE	0	/* Don't change */
-#define DSCR_CMD0_ST_CURRENT	1	/* Write current status */
-#define DSCR_CMD0_ST_CMD0	2	/* Write cmd0 with V cleared */
-#define DSCR_CMD0_ST_BYTECNT	3	/* Write remaining byte count */
-
-#define DSCR_CMD0_ST(x)		(((x) & 0x3) << 0)
-
-/* Descriptor Command 1. */
-#define DSCR_CMD1_SUPTR_MASK	(0xf << 28)	/* upper 4 bits of src addr */
-#define DSCR_CMD1_DUPTR_MASK	(0xf << 24)	/* upper 4 bits of dest addr */
-#define DSCR_CMD1_FL_MASK	(0x3 << 22)	/* Flag bits */
-#define DSCR_CMD1_BC_MASK	(0x3fffff)	/* Byte count */
-
-/* Flag description. */
-#define DSCR_CMD1_FL_MEM_STRIDE0	0
-#define DSCR_CMD1_FL_MEM_STRIDE1	1
-#define DSCR_CMD1_FL_MEM_STRIDE2	2
-
-#define DSCR_CMD1_FL(x)		(((x) & 0x3) << 22)
-
-/* Source1, 1-dimensional stride. */
-#define DSCR_SRC1_STS_MASK	(3 << 30)	/* Src xfer size */
-#define DSCR_SRC1_SAM_MASK	(3 << 28)	/* Src xfer movement */
-#define DSCR_SRC1_SB_MASK	(0x3fff << 14)	/* Block size */
-#define DSCR_SRC1_SB(x)		(((x) & 0x3fff) << 14)
-#define DSCR_SRC1_SS_MASK	(0x3fff << 0)	/* Stride */
-#define DSCR_SRC1_SS(x)		(((x) & 0x3fff) << 0)
-
-/* Dest1, 1-dimensional stride. */
-#define DSCR_DEST1_DTS_MASK	(3 << 30)	/* Dest xfer size */
-#define DSCR_DEST1_DAM_MASK	(3 << 28)	/* Dest xfer movement */
-#define DSCR_DEST1_DB_MASK	(0x3fff << 14)	/* Block size */
-#define DSCR_DEST1_DB(x)	(((x) & 0x3fff) << 14)
-#define DSCR_DEST1_DS_MASK	(0x3fff << 0)	/* Stride */
-#define DSCR_DEST1_DS(x)	(((x) & 0x3fff) << 0)
-
-#define DSCR_xTS_SIZE1		0
-#define DSCR_xTS_SIZE2		1
-#define DSCR_xTS_SIZE4		2
-#define DSCR_xTS_SIZE8		3
-#define DSCR_SRC1_STS(x)	(((x) & 3) << 30)
-#define DSCR_DEST1_DTS(x)	(((x) & 3) << 30)
-
-#define DSCR_xAM_INCREMENT	0
-#define DSCR_xAM_DECREMENT	1
-#define DSCR_xAM_STATIC		2
-#define DSCR_xAM_BURST		3
-#define DSCR_SRC1_SAM(x)	(((x) & 3) << 28)
-#define DSCR_DEST1_DAM(x)	(((x) & 3) << 28)
-
-/* The next descriptor pointer. */
-#define DSCR_NXTPTR_MASK	(0x07ffffff)
-#define DSCR_NXTPTR(x)		((x) >> 5)
-#define DSCR_GET_NXTPTR(x)	((x) << 5)
-#define DSCR_NXTPTR_MS		(1 << 27)
-
-/* The number of DBDMA channels. */
-#define NUM_DBDMA_CHANS	16
-
-/*
- * DDMA API definitions
- * FIXME: may not fit to this header file
- */
-typedef struct dbdma_device_table {
-	u32	dev_id;
-	u32	dev_flags;
-	u32	dev_tsize;
-	u32	dev_devwidth;
-	u32	dev_physaddr;		/* If FIFO */
-	u32	dev_intlevel;
-	u32	dev_intpolarity;
-} dbdev_tab_t;
-
-
-typedef struct dbdma_chan_config {
-	spinlock_t      lock;
-
-	u32			chan_flags;
-	u32			chan_index;
-	dbdev_tab_t		*chan_src;
-	dbdev_tab_t		*chan_dest;
-	au1x_dma_chan_t		*chan_ptr;
-	au1x_ddma_desc_t	*chan_desc_base;
-	au1x_ddma_desc_t	*get_ptr, *put_ptr, *cur_ptr;
-	void			*chan_callparam;
-	void			(*chan_callback)(int, void *);
-} chan_tab_t;
-
-#define DEV_FLAGS_INUSE		(1 << 0)
-#define DEV_FLAGS_ANYUSE	(1 << 1)
-#define DEV_FLAGS_OUT		(1 << 2)
-#define DEV_FLAGS_IN		(1 << 3)
-#define DEV_FLAGS_BURSTABLE	(1 << 4)
-#define DEV_FLAGS_SYNC		(1 << 5)
-/* end DDMA API definitions */
-
-/*
- * External functions for drivers to use.
- * Use this to allocate a DBDMA channel.  The device IDs are one of
- * the DSCR_CMD0 devices IDs, which is usually redefined to a more
- * meaningful name.  The 'callback' is called during DMA completion
- * interrupt.
- */
-extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
-				   void (*callback)(int, void *),
-				   void *callparam);
-
-#define DBDMA_MEM_CHAN	DSCR_CMD0_ALWAYS
-
-/* Set the device width of an in/out FIFO. */
-u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
-
-/* Allocate a ring of descriptors for DBDMA. */
-u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
-
-/* Put buffers on source/destination descriptors. */
-u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
-u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
-
-/* Get a buffer from the destination descriptor. */
-u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
-
-void au1xxx_dbdma_stop(u32 chanid);
-void au1xxx_dbdma_start(u32 chanid);
-void au1xxx_dbdma_reset(u32 chanid);
-u32 au1xxx_get_dma_residue(u32 chanid);
-
-void au1xxx_dbdma_chan_free(u32 chanid);
-void au1xxx_dbdma_dump(u32 chanid);
-
-u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
-
-u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
-extern void au1xxx_ddma_del_device(u32 devid);
-void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
-
-/*
- * Some compatibilty macros -- needed to make changes to API
- * without breaking existing drivers.
- */
-#define au1xxx_dbdma_put_source(chanid, buf, nbytes)			\
-	_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
-#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)	\
-	_au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
-#define put_source_flags(chanid, buf, nbytes, flags)			\
-	au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
-
-#define au1xxx_dbdma_put_dest(chanid, buf, nbytes)			\
-	_au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
-#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) 	\
-	_au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
-#define put_dest_flags(chanid, buf, nbytes, flags)			\
-	au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
-
-/*
- *	Flags for the put_source/put_dest functions.
- */
-#define DDMA_FLAGS_IE	(1 << 0)
-#define DDMA_FLAGS_NOIE (1 << 1)
-
-#endif /* _LANGUAGE_ASSEMBLY */
-#endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
deleted file mode 100644
index 60638b8969b..00000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00   Aug. 02 2005
- *
- * BRIEF MODULE DESCRIPTION
- * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
- *
- * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option) any later
- * version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
- * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
- *       Interface and Linux Device Driver" Application Note.
- */
-
-#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
-#define DMA_WAIT_TIMEOUT	100
-#define NUM_DESCRIPTORS 	PRD_ENTRIES
-#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
-#define NUM_DESCRIPTORS 	2
-#endif
-
-#ifndef AU1XXX_ATA_RQSIZE
-#define AU1XXX_ATA_RQSIZE	128
-#endif
-
-/* Disable Burstable-Support for DBDMA */
-#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
-#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON	0
-#endif
-
-#ifdef CONFIG_PM
-/*
- * This will enable the device to be powered up when write() or read()
- * is called. If this is not defined, the driver will return -EBUSY.
- */
-#define WAKE_ON_ACCESS 1
-
-typedef struct {
-	spinlock_t		lock;	/* Used to block on state transitions */
-	au1xxx_power_dev_t	*dev;	/* Power Managers device structure */
-	unsigned		stopped; /* Used to signal device is stopped */
-} pm_state;
-#endif
-
-typedef struct {
-	u32			tx_dev_id, rx_dev_id, target_dev_id;
-	u32			tx_chan, rx_chan;
-	void			*tx_desc_head, *rx_desc_head;
-	ide_hwif_t		*hwif;
-#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
-	ide_drive_t		*drive;
-	struct dbdma_cmd	*dma_table_cpu;
-	dma_addr_t		dma_table_dma;
-#endif
-	int			irq;
-	u32			regbase;
-#ifdef CONFIG_PM
-	pm_state		pm;
-#endif
-} _auide_hwif;
-
-/******************************************************************************/
-/* PIO Mode timing calculation :					      */
-/*									      */
-/* Static Bus Spec   ATA Spec						      */
-/*	Tcsoe	   =	t1						      */
-/*	Toecs	   =	t9						      */
-/*	Twcs	   =	t9						      */
-/*	Tcsh	   =	t2i | t2					      */
-/*	Tcsoff	   =	t2i | t2					      */
-/*	Twp	   =	t2						      */
-/*	Tcsw	   =	t1						      */
-/*	Tpm	   =	0						      */
-/*	Ta	   =	t1+t2						      */
-/******************************************************************************/
-
-#define TCSOE_MASK		(0x07 << 29)
-#define TOECS_MASK		(0x07 << 26)
-#define TWCS_MASK		(0x07 << 28)
-#define TCSH_MASK		(0x0F << 24)
-#define TCSOFF_MASK		(0x07 << 20)
-#define TWP_MASK		(0x3F << 14)
-#define TCSW_MASK		(0x0F << 10)
-#define TPM_MASK		(0x0F << 6)
-#define TA_MASK 		(0x3F << 0)
-#define TS_MASK 		(1 << 8)
-
-/* Timing parameters PIO mode 0 */
-#define SBC_IDE_PIO0_TCSOE	(0x04 << 29)
-#define SBC_IDE_PIO0_TOECS	(0x01 << 26)
-#define SBC_IDE_PIO0_TWCS	(0x02 << 28)
-#define SBC_IDE_PIO0_TCSH	(0x08 << 24)
-#define SBC_IDE_PIO0_TCSOFF	(0x07 << 20)
-#define SBC_IDE_PIO0_TWP	(0x10 << 14)
-#define SBC_IDE_PIO0_TCSW	(0x04 << 10)
-#define SBC_IDE_PIO0_TPM	(0x00 << 6)
-#define SBC_IDE_PIO0_TA 	(0x15 << 0)
-/* Timing parameters PIO mode 1 */
-#define SBC_IDE_PIO1_TCSOE	(0x03 << 29)
-#define SBC_IDE_PIO1_TOECS	(0x01 << 26)
-#define SBC_IDE_PIO1_TWCS	(0x01 << 28)
-#define SBC_IDE_PIO1_TCSH	(0x06 << 24)
-#define SBC_IDE_PIO1_TCSOFF	(0x06 << 20)
-#define SBC_IDE_PIO1_TWP	(0x08 << 14)
-#define SBC_IDE_PIO1_TCSW	(0x03 << 10)
-#define SBC_IDE_PIO1_TPM	(0x00 << 6)
-#define SBC_IDE_PIO1_TA 	(0x0B << 0)
-/* Timing parameters PIO mode 2 */
-#define SBC_IDE_PIO2_TCSOE	(0x05 << 29)
-#define SBC_IDE_PIO2_TOECS	(0x01 << 26)
-#define SBC_IDE_PIO2_TWCS	(0x01 << 28)
-#define SBC_IDE_PIO2_TCSH	(0x07 << 24)
-#define SBC_IDE_PIO2_TCSOFF	(0x07 << 20)
-#define SBC_IDE_PIO2_TWP	(0x1F << 14)
-#define SBC_IDE_PIO2_TCSW	(0x05 << 10)
-#define SBC_IDE_PIO2_TPM	(0x00 << 6)
-#define SBC_IDE_PIO2_TA 	(0x22 << 0)
-/* Timing parameters PIO mode 3 */
-#define SBC_IDE_PIO3_TCSOE	(0x05 << 29)
-#define SBC_IDE_PIO3_TOECS	(0x01 << 26)
-#define SBC_IDE_PIO3_TWCS	(0x01 << 28)
-#define SBC_IDE_PIO3_TCSH	(0x0D << 24)
-#define SBC_IDE_PIO3_TCSOFF	(0x0D << 20)
-#define SBC_IDE_PIO3_TWP	(0x15 << 14)
-#define SBC_IDE_PIO3_TCSW	(0x05 << 10)
-#define SBC_IDE_PIO3_TPM	(0x00 << 6)
-#define SBC_IDE_PIO3_TA 	(0x1A << 0)
-/* Timing parameters PIO mode 4 */
-#define SBC_IDE_PIO4_TCSOE	(0x04 << 29)
-#define SBC_IDE_PIO4_TOECS	(0x01 << 26)
-#define SBC_IDE_PIO4_TWCS	(0x01 << 28)
-#define SBC_IDE_PIO4_TCSH	(0x04 << 24)
-#define SBC_IDE_PIO4_TCSOFF	(0x04 << 20)
-#define SBC_IDE_PIO4_TWP	(0x0D << 14)
-#define SBC_IDE_PIO4_TCSW	(0x03 << 10)
-#define SBC_IDE_PIO4_TPM	(0x00 << 6)
-#define SBC_IDE_PIO4_TA 	(0x12 << 0)
-/* Timing parameters MDMA mode 0 */
-#define SBC_IDE_MDMA0_TCSOE	(0x03 << 29)
-#define SBC_IDE_MDMA0_TOECS	(0x01 << 26)
-#define SBC_IDE_MDMA0_TWCS	(0x01 << 28)
-#define SBC_IDE_MDMA0_TCSH	(0x07 << 24)
-#define SBC_IDE_MDMA0_TCSOFF	(0x07 << 20)
-#define SBC_IDE_MDMA0_TWP	(0x0C << 14)
-#define SBC_IDE_MDMA0_TCSW	(0x03 << 10)
-#define SBC_IDE_MDMA0_TPM	(0x00 << 6)
-#define SBC_IDE_MDMA0_TA	(0x0F << 0)
-/* Timing parameters MDMA mode 1 */
-#define SBC_IDE_MDMA1_TCSOE	(0x05 << 29)
-#define SBC_IDE_MDMA1_TOECS	(0x01 << 26)
-#define SBC_IDE_MDMA1_TWCS	(0x01 << 28)
-#define SBC_IDE_MDMA1_TCSH	(0x05 << 24)
-#define SBC_IDE_MDMA1_TCSOFF	(0x05 << 20)
-#define SBC_IDE_MDMA1_TWP	(0x0F << 14)
-#define SBC_IDE_MDMA1_TCSW	(0x05 << 10)
-#define SBC_IDE_MDMA1_TPM	(0x00 << 6)
-#define SBC_IDE_MDMA1_TA	(0x15 << 0)
-/* Timing parameters MDMA mode 2 */
-#define SBC_IDE_MDMA2_TCSOE	(0x04 << 29)
-#define SBC_IDE_MDMA2_TOECS	(0x01 << 26)
-#define SBC_IDE_MDMA2_TWCS	(0x01 << 28)
-#define SBC_IDE_MDMA2_TCSH	(0x04 << 24)
-#define SBC_IDE_MDMA2_TCSOFF	(0x04 << 20)
-#define SBC_IDE_MDMA2_TWP	(0x0D << 14)
-#define SBC_IDE_MDMA2_TCSW	(0x04 << 10)
-#define SBC_IDE_MDMA2_TPM	(0x00 << 6)
-#define SBC_IDE_MDMA2_TA	(0x12 << 0)
-
-#define SBC_IDE_TIMING(mode) \
-	(SBC_IDE_##mode##_TWCS | \
-	 SBC_IDE_##mode##_TCSH | \
-	 SBC_IDE_##mode##_TCSOFF | \
-	 SBC_IDE_##mode##_TWP | \
-	 SBC_IDE_##mode##_TCSW | \
-	 SBC_IDE_##mode##_TPM | \
-	 SBC_IDE_##mode##_TA)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
deleted file mode 100644
index 892b7f168eb..00000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *	Include file for Alchemy Semiconductor's Au1k CPU.
- *
- * Copyright 2004 Embedded Edge, LLC
- *	dan@embeddededge.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/* Specifics for the Au1xxx Programmable Serial Controllers, first
- * seen in the AU1550 part.
- */
-#ifndef _AU1000_PSC_H_
-#define _AU1000_PSC_H_
-
-/* The PSC base addresses.  */
-#ifdef CONFIG_SOC_AU1550
-#define PSC0_BASE_ADDR		0xb1a00000
-#define PSC1_BASE_ADDR		0xb1b00000
-#define PSC2_BASE_ADDR		0xb0a00000
-#define PSC3_BASE_ADDR		0xb0b00000
-#endif
-
-#ifdef CONFIG_SOC_AU1200
-#define PSC0_BASE_ADDR		0xb1a00000
-#define PSC1_BASE_ADDR		0xb1b00000
-#endif
-
-/*
- * The PSC select and control registers are common to all protocols.
- */
-#define PSC_SEL_OFFSET		0x00000000
-#define PSC_CTRL_OFFSET		0x00000004
-
-#define PSC_SEL_CLK_MASK	(3 << 4)
-#define PSC_SEL_CLK_INTCLK	(0 << 4)
-#define PSC_SEL_CLK_EXTCLK	(1 << 4)
-#define PSC_SEL_CLK_SERCLK	(2 << 4)
-
-#define PSC_SEL_PS_MASK		0x00000007
-#define PSC_SEL_PS_DISABLED	0
-#define PSC_SEL_PS_SPIMODE	2
-#define PSC_SEL_PS_I2SMODE	3
-#define PSC_SEL_PS_AC97MODE	4
-#define PSC_SEL_PS_SMBUSMODE	5
-
-#define PSC_CTRL_DISABLE	0
-#define PSC_CTRL_SUSPEND	2
-#define PSC_CTRL_ENABLE 	3
-
-/* AC97 Registers. */
-#define PSC_AC97CFG_OFFSET	0x00000008
-#define PSC_AC97MSK_OFFSET	0x0000000c
-#define PSC_AC97PCR_OFFSET	0x00000010
-#define PSC_AC97STAT_OFFSET	0x00000014
-#define PSC_AC97EVNT_OFFSET	0x00000018
-#define PSC_AC97TXRX_OFFSET	0x0000001c
-#define PSC_AC97CDC_OFFSET	0x00000020
-#define PSC_AC97RST_OFFSET	0x00000024
-#define PSC_AC97GPO_OFFSET	0x00000028
-#define PSC_AC97GPI_OFFSET	0x0000002c
-
-#define AC97_PSC_SEL		(AC97_PSC_BASE + PSC_SEL_OFFSET)
-#define AC97_PSC_CTRL		(AC97_PSC_BASE + PSC_CTRL_OFFSET)
-#define PSC_AC97CFG		(AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
-#define PSC_AC97MSK		(AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
-#define PSC_AC97PCR		(AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
-#define PSC_AC97STAT		(AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
-#define PSC_AC97EVNT		(AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
-#define PSC_AC97TXRX		(AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
-#define PSC_AC97CDC		(AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
-#define PSC_AC97RST		(AC97_PSC_BASE + PSC_AC97RST_OFFSET)
-#define PSC_AC97GPO		(AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
-#define PSC_AC97GPI		(AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
-
-/* AC97 Config Register. */
-#define PSC_AC97CFG_RT_MASK	(3 << 30)
-#define PSC_AC97CFG_RT_FIFO1	(0 << 30)
-#define PSC_AC97CFG_RT_FIFO2	(1 << 30)
-#define PSC_AC97CFG_RT_FIFO4	(2 << 30)
-#define PSC_AC97CFG_RT_FIFO8	(3 << 30)
-
-#define PSC_AC97CFG_TT_MASK	(3 << 28)
-#define PSC_AC97CFG_TT_FIFO1	(0 << 28)
-#define PSC_AC97CFG_TT_FIFO2	(1 << 28)
-#define PSC_AC97CFG_TT_FIFO4	(2 << 28)
-#define PSC_AC97CFG_TT_FIFO8	(3 << 28)
-
-#define PSC_AC97CFG_DD_DISABLE	(1 << 27)
-#define PSC_AC97CFG_DE_ENABLE	(1 << 26)
-#define PSC_AC97CFG_SE_ENABLE	(1 << 25)
-
-#define PSC_AC97CFG_LEN_MASK	(0xf << 21)
-#define PSC_AC97CFG_TXSLOT_MASK	(0x3ff << 11)
-#define PSC_AC97CFG_RXSLOT_MASK	(0x3ff << 1)
-#define PSC_AC97CFG_GE_ENABLE	(1)
-
-/* Enable slots 3-12. */
-#define PSC_AC97CFG_TXSLOT_ENA(x)	(1 << (((x) - 3) + 11))
-#define PSC_AC97CFG_RXSLOT_ENA(x)	(1 << (((x) - 3) + 1))
-
-/*
- * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
- * The only sensible numbers are 7, 9, or possibly 11.  Nah, just do the
- * arithmetic in the macro.
- */
-#define PSC_AC97CFG_SET_LEN(x)	(((((x) - 2) / 2) & 0xf) << 21)
-#define PSC_AC97CFG_GET_LEN(x)	(((((x) >> 21) & 0xf) * 2) + 2)
-
-/* AC97 Mask Register. */
-#define PSC_AC97MSK_GR		(1 << 25)
-#define PSC_AC97MSK_CD		(1 << 24)
-#define PSC_AC97MSK_RR		(1 << 13)
-#define PSC_AC97MSK_RO		(1 << 12)
-#define PSC_AC97MSK_RU		(1 << 11)
-#define PSC_AC97MSK_TR		(1 << 10)
-#define PSC_AC97MSK_TO		(1 << 9)
-#define PSC_AC97MSK_TU		(1 << 8)
-#define PSC_AC97MSK_RD		(1 << 5)
-#define PSC_AC97MSK_TD		(1 << 4)
-#define PSC_AC97MSK_ALLMASK	(PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
-				 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
-				 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
-				 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
-				 PSC_AC97MSK_RD | PSC_AC97MSK_TD)
-
-/* AC97 Protocol Control Register. */
-#define PSC_AC97PCR_RC		(1 << 6)
-#define PSC_AC97PCR_RP		(1 << 5)
-#define PSC_AC97PCR_RS		(1 << 4)
-#define PSC_AC97PCR_TC		(1 << 2)
-#define PSC_AC97PCR_TP		(1 << 1)
-#define PSC_AC97PCR_TS		(1 << 0)
-
-/* AC97 Status register (read only). */
-#define PSC_AC97STAT_CB		(1 << 26)
-#define PSC_AC97STAT_CP		(1 << 25)
-#define PSC_AC97STAT_CR		(1 << 24)
-#define PSC_AC97STAT_RF		(1 << 13)
-#define PSC_AC97STAT_RE		(1 << 12)
-#define PSC_AC97STAT_RR		(1 << 11)
-#define PSC_AC97STAT_TF		(1 << 10)
-#define PSC_AC97STAT_TE		(1 << 9)
-#define PSC_AC97STAT_TR		(1 << 8)
-#define PSC_AC97STAT_RB		(1 << 5)
-#define PSC_AC97STAT_TB		(1 << 4)
-#define PSC_AC97STAT_DI		(1 << 2)
-#define PSC_AC97STAT_DR		(1 << 1)
-#define PSC_AC97STAT_SR		(1 << 0)
-
-/* AC97 Event Register. */
-#define PSC_AC97EVNT_GR		(1 << 25)
-#define PSC_AC97EVNT_CD		(1 << 24)
-#define PSC_AC97EVNT_RR		(1 << 13)
-#define PSC_AC97EVNT_RO		(1 << 12)
-#define PSC_AC97EVNT_RU		(1 << 11)
-#define PSC_AC97EVNT_TR		(1 << 10)
-#define PSC_AC97EVNT_TO		(1 << 9)
-#define PSC_AC97EVNT_TU		(1 << 8)
-#define PSC_AC97EVNT_RD		(1 << 5)
-#define PSC_AC97EVNT_TD		(1 << 4)
-
-/* CODEC Command Register. */
-#define PSC_AC97CDC_RD		(1 << 25)
-#define PSC_AC97CDC_ID_MASK	(3 << 23)
-#define PSC_AC97CDC_INDX_MASK	(0x7f << 16)
-#define PSC_AC97CDC_ID(x)	(((x) & 0x03) << 23)
-#define PSC_AC97CDC_INDX(x)	(((x) & 0x7f) << 16)
-
-/* AC97 Reset Control Register. */
-#define PSC_AC97RST_RST		(1 << 1)
-#define PSC_AC97RST_SNC		(1 << 0)
-
-/* PSC in I2S Mode. */
-typedef struct	psc_i2s {
-	u32	psc_sel;
-	u32	psc_ctrl;
-	u32	psc_i2scfg;
-	u32	psc_i2smsk;
-	u32	psc_i2spcr;
-	u32	psc_i2sstat;
-	u32	psc_i2sevent;
-	u32	psc_i2stxrx;
-	u32	psc_i2sudf;
-} psc_i2s_t;
-
-#define PSC_I2SCFG_OFFSET	0x08
-#define PSC_I2SMASK_OFFSET	0x0C
-#define PSC_I2SPCR_OFFSET	0x10
-#define PSC_I2SSTAT_OFFSET	0x14
-#define PSC_I2SEVENT_OFFSET	0x18
-#define PSC_I2SRXTX_OFFSET	0x1C
-#define PSC_I2SUDF_OFFSET	0x20
-
-/* I2S Config Register. */
-#define PSC_I2SCFG_RT_MASK	(3 << 30)
-#define PSC_I2SCFG_RT_FIFO1	(0 << 30)
-#define PSC_I2SCFG_RT_FIFO2	(1 << 30)
-#define PSC_I2SCFG_RT_FIFO4	(2 << 30)
-#define PSC_I2SCFG_RT_FIFO8	(3 << 30)
-
-#define PSC_I2SCFG_TT_MASK	(3 << 28)
-#define PSC_I2SCFG_TT_FIFO1	(0 << 28)
-#define PSC_I2SCFG_TT_FIFO2	(1 << 28)
-#define PSC_I2SCFG_TT_FIFO4	(2 << 28)
-#define PSC_I2SCFG_TT_FIFO8	(3 << 28)
-
-#define PSC_I2SCFG_DD_DISABLE	(1 << 27)
-#define PSC_I2SCFG_DE_ENABLE	(1 << 26)
-#define PSC_I2SCFG_SET_WS(x)	(((((x) / 2) - 1) & 0x7f) << 16)
-#define PSC_I2SCFG_WS(n)	((n & 0xFF) << 16)
-#define PSC_I2SCFG_WS_MASK	(PSC_I2SCFG_WS(0x3F))
-#define PSC_I2SCFG_WI		(1 << 15)
-
-#define PSC_I2SCFG_DIV_MASK	(3 << 13)
-#define PSC_I2SCFG_DIV2		(0 << 13)
-#define PSC_I2SCFG_DIV4		(1 << 13)
-#define PSC_I2SCFG_DIV8		(2 << 13)
-#define PSC_I2SCFG_DIV16	(3 << 13)
-
-#define PSC_I2SCFG_BI		(1 << 12)
-#define PSC_I2SCFG_BUF		(1 << 11)
-#define PSC_I2SCFG_MLJ		(1 << 10)
-#define PSC_I2SCFG_XM		(1 << 9)
-
-/* The word length equation is simply LEN+1. */
-#define PSC_I2SCFG_SET_LEN(x)	((((x) - 1) & 0x1f) << 4)
-#define PSC_I2SCFG_GET_LEN(x)	((((x) >> 4) & 0x1f) + 1)
-
-#define PSC_I2SCFG_LB		(1 << 2)
-#define PSC_I2SCFG_MLF		(1 << 1)
-#define PSC_I2SCFG_MS		(1 << 0)
-
-/* I2S Mask Register. */
-#define PSC_I2SMSK_RR		(1 << 13)
-#define PSC_I2SMSK_RO		(1 << 12)
-#define PSC_I2SMSK_RU		(1 << 11)
-#define PSC_I2SMSK_TR		(1 << 10)
-#define PSC_I2SMSK_TO		(1 << 9)
-#define PSC_I2SMSK_TU		(1 << 8)
-#define PSC_I2SMSK_RD		(1 << 5)
-#define PSC_I2SMSK_TD		(1 << 4)
-#define PSC_I2SMSK_ALLMASK	(PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
-				 PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
-				 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
-				 PSC_I2SMSK_RD | PSC_I2SMSK_TD)
-
-/* I2S Protocol Control Register. */
-#define PSC_I2SPCR_RC		(1 << 6)
-#define PSC_I2SPCR_RP		(1 << 5)
-#define PSC_I2SPCR_RS		(1 << 4)
-#define PSC_I2SPCR_TC		(1 << 2)
-#define PSC_I2SPCR_TP		(1 << 1)
-#define PSC_I2SPCR_TS		(1 << 0)
-
-/* I2S Status register (read only). */
-#define PSC_I2SSTAT_RF		(1 << 13)
-#define PSC_I2SSTAT_RE		(1 << 12)
-#define PSC_I2SSTAT_RR		(1 << 11)
-#define PSC_I2SSTAT_TF		(1 << 10)
-#define PSC_I2SSTAT_TE		(1 << 9)
-#define PSC_I2SSTAT_TR		(1 << 8)
-#define PSC_I2SSTAT_RB		(1 << 5)
-#define PSC_I2SSTAT_TB		(1 << 4)
-#define PSC_I2SSTAT_DI		(1 << 2)
-#define PSC_I2SSTAT_DR		(1 << 1)
-#define PSC_I2SSTAT_SR		(1 << 0)
-
-/* I2S Event Register. */
-#define PSC_I2SEVNT_RR		(1 << 13)
-#define PSC_I2SEVNT_RO		(1 << 12)
-#define PSC_I2SEVNT_RU		(1 << 11)
-#define PSC_I2SEVNT_TR		(1 << 10)
-#define PSC_I2SEVNT_TO		(1 << 9)
-#define PSC_I2SEVNT_TU		(1 << 8)
-#define PSC_I2SEVNT_RD		(1 << 5)
-#define PSC_I2SEVNT_TD		(1 << 4)
-
-/* PSC in SPI Mode. */
-typedef struct	psc_spi {
-	u32	psc_sel;
-	u32	psc_ctrl;
-	u32	psc_spicfg;
-	u32	psc_spimsk;
-	u32	psc_spipcr;
-	u32	psc_spistat;
-	u32	psc_spievent;
-	u32	psc_spitxrx;
-} psc_spi_t;
-
-/* SPI Config Register. */
-#define PSC_SPICFG_RT_MASK	(3 << 30)
-#define PSC_SPICFG_RT_FIFO1	(0 << 30)
-#define PSC_SPICFG_RT_FIFO2	(1 << 30)
-#define PSC_SPICFG_RT_FIFO4	(2 << 30)
-#define PSC_SPICFG_RT_FIFO8	(3 << 30)
-
-#define PSC_SPICFG_TT_MASK	(3 << 28)
-#define PSC_SPICFG_TT_FIFO1	(0 << 28)
-#define PSC_SPICFG_TT_FIFO2	(1 << 28)
-#define PSC_SPICFG_TT_FIFO4	(2 << 28)
-#define PSC_SPICFG_TT_FIFO8	(3 << 28)
-
-#define PSC_SPICFG_DD_DISABLE	(1 << 27)
-#define PSC_SPICFG_DE_ENABLE	(1 << 26)
-#define PSC_SPICFG_CLR_BAUD(x)	((x) & ~((0x3f) << 15))
-#define PSC_SPICFG_SET_BAUD(x)	(((x) & 0x3f) << 15)
-
-#define PSC_SPICFG_SET_DIV(x)	(((x) & 0x03) << 13)
-#define PSC_SPICFG_DIV2		0
-#define PSC_SPICFG_DIV4		1
-#define PSC_SPICFG_DIV8		2
-#define PSC_SPICFG_DIV16	3
-
-#define PSC_SPICFG_BI		(1 << 12)
-#define PSC_SPICFG_PSE		(1 << 11)
-#define PSC_SPICFG_CGE		(1 << 10)
-#define PSC_SPICFG_CDE		(1 << 9)
-
-#define PSC_SPICFG_CLR_LEN(x)	((x) & ~((0x1f) << 4))
-#define PSC_SPICFG_SET_LEN(x)	(((x-1) & 0x1f) << 4)
-
-#define PSC_SPICFG_LB		(1 << 3)
-#define PSC_SPICFG_MLF		(1 << 1)
-#define PSC_SPICFG_MO		(1 << 0)
-
-/* SPI Mask Register. */
-#define PSC_SPIMSK_MM		(1 << 16)
-#define PSC_SPIMSK_RR		(1 << 13)
-#define PSC_SPIMSK_RO		(1 << 12)
-#define PSC_SPIMSK_RU		(1 << 11)
-#define PSC_SPIMSK_TR		(1 << 10)
-#define PSC_SPIMSK_TO		(1 << 9)
-#define PSC_SPIMSK_TU		(1 << 8)
-#define PSC_SPIMSK_SD		(1 << 5)
-#define PSC_SPIMSK_MD		(1 << 4)
-#define PSC_SPIMSK_ALLMASK	(PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
-				 PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
-				 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
-				 PSC_SPIMSK_MD)
-
-/* SPI Protocol Control Register. */
-#define PSC_SPIPCR_RC		(1 << 6)
-#define PSC_SPIPCR_SP		(1 << 5)
-#define PSC_SPIPCR_SS		(1 << 4)
-#define PSC_SPIPCR_TC		(1 << 2)
-#define PSC_SPIPCR_MS		(1 << 0)
-
-/* SPI Status register (read only). */
-#define PSC_SPISTAT_RF		(1 << 13)
-#define PSC_SPISTAT_RE		(1 << 12)
-#define PSC_SPISTAT_RR		(1 << 11)
-#define PSC_SPISTAT_TF		(1 << 10)
-#define PSC_SPISTAT_TE		(1 << 9)
-#define PSC_SPISTAT_TR		(1 << 8)
-#define PSC_SPISTAT_SB		(1 << 5)
-#define PSC_SPISTAT_MB		(1 << 4)
-#define PSC_SPISTAT_DI		(1 << 2)
-#define PSC_SPISTAT_DR		(1 << 1)
-#define PSC_SPISTAT_SR		(1 << 0)
-
-/* SPI Event Register. */
-#define PSC_SPIEVNT_MM		(1 << 16)
-#define PSC_SPIEVNT_RR		(1 << 13)
-#define PSC_SPIEVNT_RO		(1 << 12)
-#define PSC_SPIEVNT_RU		(1 << 11)
-#define PSC_SPIEVNT_TR		(1 << 10)
-#define PSC_SPIEVNT_TO		(1 << 9)
-#define PSC_SPIEVNT_TU		(1 << 8)
-#define PSC_SPIEVNT_SD		(1 << 5)
-#define PSC_SPIEVNT_MD		(1 << 4)
-
-/* Transmit register control. */
-#define PSC_SPITXRX_LC		(1 << 29)
-#define PSC_SPITXRX_SR		(1 << 28)
-
-/* PSC in SMBus (I2C) Mode. */
-typedef struct	psc_smb {
-	u32	psc_sel;
-	u32	psc_ctrl;
-	u32	psc_smbcfg;
-	u32	psc_smbmsk;
-	u32	psc_smbpcr;
-	u32	psc_smbstat;
-	u32	psc_smbevnt;
-	u32	psc_smbtxrx;
-	u32	psc_smbtmr;
-} psc_smb_t;
-
-/* SMBus Config Register. */
-#define PSC_SMBCFG_RT_MASK	(3 << 30)
-#define PSC_SMBCFG_RT_FIFO1	(0 << 30)
-#define PSC_SMBCFG_RT_FIFO2	(1 << 30)
-#define PSC_SMBCFG_RT_FIFO4	(2 << 30)
-#define PSC_SMBCFG_RT_FIFO8	(3 << 30)
-
-#define PSC_SMBCFG_TT_MASK	(3 << 28)
-#define PSC_SMBCFG_TT_FIFO1	(0 << 28)
-#define PSC_SMBCFG_TT_FIFO2	(1 << 28)
-#define PSC_SMBCFG_TT_FIFO4	(2 << 28)
-#define PSC_SMBCFG_TT_FIFO8	(3 << 28)
-
-#define PSC_SMBCFG_DD_DISABLE	(1 << 27)
-#define PSC_SMBCFG_DE_ENABLE	(1 << 26)
-
-#define PSC_SMBCFG_SET_DIV(x)	(((x) & 0x03) << 13)
-#define PSC_SMBCFG_DIV2		0
-#define PSC_SMBCFG_DIV4		1
-#define PSC_SMBCFG_DIV8		2
-#define PSC_SMBCFG_DIV16	3
-
-#define PSC_SMBCFG_GCE		(1 << 9)
-#define PSC_SMBCFG_SFM		(1 << 8)
-
-#define PSC_SMBCFG_SET_SLV(x)	(((x) & 0x7f) << 1)
-
-/* SMBus Mask Register. */
-#define PSC_SMBMSK_DN		(1 << 30)
-#define PSC_SMBMSK_AN		(1 << 29)
-#define PSC_SMBMSK_AL		(1 << 28)
-#define PSC_SMBMSK_RR		(1 << 13)
-#define PSC_SMBMSK_RO		(1 << 12)
-#define PSC_SMBMSK_RU		(1 << 11)
-#define PSC_SMBMSK_TR		(1 << 10)
-#define PSC_SMBMSK_TO		(1 << 9)
-#define PSC_SMBMSK_TU		(1 << 8)
-#define PSC_SMBMSK_SD		(1 << 5)
-#define PSC_SMBMSK_MD		(1 << 4)
-#define PSC_SMBMSK_ALLMASK	(PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
-				 PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
-				 PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
-				 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
-				 PSC_SMBMSK_MD)
-
-/* SMBus Protocol Control Register. */
-#define PSC_SMBPCR_DC		(1 << 2)
-#define PSC_SMBPCR_MS		(1 << 0)
-
-/* SMBus Status register (read only). */
-#define PSC_SMBSTAT_BB		(1 << 28)
-#define PSC_SMBSTAT_RF		(1 << 13)
-#define PSC_SMBSTAT_RE		(1 << 12)
-#define PSC_SMBSTAT_RR		(1 << 11)
-#define PSC_SMBSTAT_TF		(1 << 10)
-#define PSC_SMBSTAT_TE		(1 << 9)
-#define PSC_SMBSTAT_TR		(1 << 8)
-#define PSC_SMBSTAT_SB		(1 << 5)
-#define PSC_SMBSTAT_MB		(1 << 4)
-#define PSC_SMBSTAT_DI		(1 << 2)
-#define PSC_SMBSTAT_DR		(1 << 1)
-#define PSC_SMBSTAT_SR		(1 << 0)
-
-/* SMBus Event Register. */
-#define PSC_SMBEVNT_DN		(1 << 30)
-#define PSC_SMBEVNT_AN		(1 << 29)
-#define PSC_SMBEVNT_AL		(1 << 28)
-#define PSC_SMBEVNT_RR		(1 << 13)
-#define PSC_SMBEVNT_RO		(1 << 12)
-#define PSC_SMBEVNT_RU		(1 << 11)
-#define PSC_SMBEVNT_TR		(1 << 10)
-#define PSC_SMBEVNT_TO		(1 << 9)
-#define PSC_SMBEVNT_TU		(1 << 8)
-#define PSC_SMBEVNT_SD		(1 << 5)
-#define PSC_SMBEVNT_MD		(1 << 4)
-#define PSC_SMBEVNT_ALLCLR	(PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
-				 PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
-				 PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
-				 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
-				 PSC_SMBEVNT_MD)
-
-/* Transmit register control. */
-#define PSC_SMBTXRX_RSR		(1 << 28)
-#define PSC_SMBTXRX_STP		(1 << 29)
-#define PSC_SMBTXRX_DATAMASK	0xff
-
-/* SMBus protocol timers register. */
-#define PSC_SMBTMR_SET_TH(x)	(((x) & 0x03) << 30)
-#define PSC_SMBTMR_SET_PS(x)	(((x) & 0x1f) << 25)
-#define PSC_SMBTMR_SET_PU(x)	(((x) & 0x1f) << 20)
-#define PSC_SMBTMR_SET_SH(x)	(((x) & 0x1f) << 15)
-#define PSC_SMBTMR_SET_SU(x)	(((x) & 0x1f) << 10)
-#define PSC_SMBTMR_SET_CL(x)	(((x) & 0x1f) << 5)
-#define PSC_SMBTMR_SET_CH(x)	(((x) & 0x1f) << 0)
-
-#endif /* _AU1000_PSC_H_ */
diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h
deleted file mode 100644
index 2dc61e009a0..00000000000
--- a/include/asm-mips/mach-au1x00/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _AU1XXX_GPIO_H_
-#define _AU1XXX_GPIO_H_
-
-#include <linux/types.h>
-
-#define AU1XXX_GPIO_BASE	200
-
-struct au1x00_gpio2 {
-	u32	dir;
-	u32	reserved;
-	u32	output;
-	u32	pinstate;
-	u32	inten;
-	u32	enable;
-};
-
-extern int au1xxx_gpio_get_value(unsigned gpio);
-extern void au1xxx_gpio_set_value(unsigned gpio, int value);
-extern int au1xxx_gpio_direction_input(unsigned gpio);
-extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
-
-
-/* Wrappers for the arch-neutral GPIO API */
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-	/* Not yet implemented */
-	return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-	/* Not yet implemented */
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-	return au1xxx_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-	return au1xxx_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-	return au1xxx_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-	au1xxx_gpio_set_value(gpio, value);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-	return gpio;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-	return irq;
-}
-
-/* For cansleep */
-#include <asm-generic/gpio.h>
-
-#endif /* _AU1XXX_GPIO_H_ */
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h
deleted file mode 100644
index 364cea2dc71..00000000000
--- a/include/asm-mips/mach-au1x00/ioremap.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *	include/asm-mips/mach-au1x00/ioremap.h
- *
- *	This program is free software; you can redistribute it and/or
- *	modify it under the terms of the GNU General Public License
- *	as published by the Free Software Foundation; either version
- *	2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MACH_AU1X00_IOREMAP_H
-#define __ASM_MACH_AU1X00_IOREMAP_H
-
-#include <linux/types.h>
-
-#ifdef CONFIG_64BIT_PHYS_ADDR
-extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
-#else
-static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-{
-	return phys_addr;
-}
-#endif
-
-/*
- * Allow physical addresses to be fixed up to help 36-bit peripherals.
- */
-static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-{
-	return __fixup_bigphys_addr(phys_addr, size);
-}
-
-static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
-	unsigned long flags)
-{
-	return NULL;
-}
-
-static inline int plat_iounmap(const volatile void __iomem *addr)
-{
-	return 0;
-}
-
-#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
diff --git a/include/asm-mips/mach-au1x00/prom.h b/include/asm-mips/mach-au1x00/prom.h
deleted file mode 100644
index e38715577c5..00000000000
--- a/include/asm-mips/mach-au1x00/prom.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __AU1X00_PROM_H
-#define __AU1X00_PROM_H
-
-extern int prom_argc;
-extern char **prom_argv;
-extern char **prom_envp;
-
-extern void prom_init_cmdline(void);
-extern char *prom_getcmdline(void);
-extern char *prom_getenv(char *envname);
-extern int prom_get_ethernet_addr(char *ethernet_addr);
-
-#endif
diff --git a/include/asm-mips/mach-au1x00/war.h b/include/asm-mips/mach-au1x00/war.h
deleted file mode 100644
index dd57d03d68b..00000000000
--- a/include/asm-mips/mach-au1x00/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H
-#define __ASM_MIPS_MACH_AU1X00_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR	0
-#define R4600_V1_HIT_CACHEOP_WAR	0
-#define R4600_V2_HIT_CACHEOP_WAR	0
-#define R5432_CP0_INTERRUPT_WAR		0
-#define BCM1250_M3_WAR			0
-#define SIBYTE_1956_WAR			0
-#define MIPS4K_ICACHE_REFILL_WAR	0
-#define MIPS_CACHE_SYNC_WAR		0
-#define TX49XX_ICACHE_INDEX_INV_WAR	0
-#define RM9000_CDEX_SMP_WAR		0
-#define ICACHE_REFILLS_WORKAROUND_WAR	0
-#define R10000_LLSC_WAR			0
-#define MIPS34K_MISSED_ITLB_WAR		0
-
-#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */