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authorRalf Baechle <ralf@linux-mips.org>2008-07-15 18:44:34 +0100
committerRalf Baechle <ralf@linux-mips.org>2008-07-15 18:44:34 +0100
commit315806cb19f9d375dccbc2d60fa14e16afdcd5ac (patch)
treeeffe89f2f8d49bf62018ad5717a0d7c8c5725277 /include/asm-mips/mach-malta/war.h
parenteda49eeebf263f3a34f6968959fc2e4825b42beb (diff)
[MIPS] Malta: Cleanup organization of code into directories.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-malta/war.h')
-rw-r--r--include/asm-mips/mach-malta/war.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/asm-mips/mach-malta/war.h b/include/asm-mips/mach-malta/war.h
new file mode 100644
index 00000000000..7c6931d5f45
--- /dev/null
+++ b/include/asm-mips/mach-malta/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
+#define __ASM_MIPS_MACH_MIPS_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 1
+#define MIPS_CACHE_SYNC_WAR 1
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 1
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */