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| author | Ingo Molnar <mingo@elte.hu> | 2009-01-11 15:34:05 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-01-11 15:34:05 +0100 |
| commit | d19b85db9d5c44a4c21dcb10d6fbadaa4425ab2a (patch) | |
| tree | 250be7a5a29069f7d1f4524fa45ab0e988833025 /include/asm-xtensa/cache.h | |
| parent | 490dea45d00f01847ebebd007685d564aaf2cd98 (diff) | |
| parent | c59765042f53a79a7a65585042ff463b69cb248c (diff) | |
Merge commit 'v2.6.29-rc1' into timers/urgent
Diffstat (limited to 'include/asm-xtensa/cache.h')
| -rw-r--r-- | include/asm-xtensa/cache.h | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h deleted file mode 100644 index 3bba2a540cf..00000000000 --- a/include/asm-xtensa/cache.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * include/asm-xtensa/cache.h - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * (C) 2001 - 2005 Tensilica Inc. - */ - -#ifndef _XTENSA_CACHE_H -#define _XTENSA_CACHE_H - -#include <asm/variant/core.h> - -#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH -#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE -#define SMP_CACHE_BYTES L1_CACHE_BYTES - -#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) -#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) -#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) -#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) - -/* Maximum cache size per way. */ -#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE -# define CACHE_WAY_SIZE DCACHE_WAY_SIZE -#else -# define CACHE_WAY_SIZE ICACHE_WAY_SIZE -#endif - - -#endif /* _XTENSA_CACHE_H */ |