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authorShaik Ameer Basha <shaik.ameer@samsung.com>2014-05-08 16:57:52 +0530
committerTomasz Figa <t.figa@samsung.com>2014-05-14 19:40:18 +0200
commit02932381ca1d9ab894c893b28fed288d6bae011b (patch)
tree434f55d439c3d1a3319d29ecb119c7e9ffc6a86a /include/dt-bindings
parent3a767b35c6c2f2e5f75e22a429b4d6d8c6736626 (diff)
clk: samsung: exynos5420: update clocks for GSCL and MSCL blocks
This patch adds the missing GSCL and MSCL block clocks and corrects some wrong parent-child relationships. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/exynos5420.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index bddf5496fef..6e22fddb013 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -159,7 +159,7 @@
#define CLK_GSCL_WB 464
#define CLK_GSCL0 465
#define CLK_GSCL1 466
-#define CLK_CLK_3AA 467
+#define CLK_FIMC_3AA 467
#define CLK_ACLK266_G2D 470
#define CLK_SSS 471
#define CLK_SLIM_SSS 472
@@ -172,6 +172,8 @@
#define CLK_SMMU_FIMCL1 493
#define CLK_SMMU_FIMCL3 494
#define CLK_FIMC_LITE3 495
+#define CLK_FIMC_LITE0 496
+#define CLK_FIMC_LITE1 497
#define CLK_ACLK_G3D 500
#define CLK_G3D 501
#define CLK_SMMU_MIXER 502