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authorViresh Kumar <viresh.kumar@st.com>2011-03-03 15:47:22 +0530
committerVinod Koul <vinod.koul@intel.com>2011-03-07 01:12:28 +0530
commit93317e8e35b77633d589fe0e132291195757d785 (patch)
treec3419c1a02e3952506ca0af281f9f9c5bc52888d /include/linux/dw_dmac.h
parentb0c3130d69bda5cd91aa3b3f08e7878df49fde69 (diff)
dw_dmac: Pass Channel Priority from platform_data
In Synopsys designware, channel priority is programmable. This patch adds support for passing channel priority through platform data. By default Ascending channel priority will be followed, i.e. channel 0 will get highest priority and channel 7 will get lowest. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'include/linux/dw_dmac.h')
-rw-r--r--include/linux/dw_dmac.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index a18c498984d..64c76da571e 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -25,6 +25,9 @@ struct dw_dma_platform_data {
#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
unsigned char chan_allocation_order;
+#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
+#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
+ unsigned char chan_priority;
};
/**
@@ -70,7 +73,6 @@ struct dw_dma_slave {
#define DWC_CFGH_DST_PER(x) ((x) << 11)
/* Platform-configurable bits in CFG_LO */
-#define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */
#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
#define DWC_CFGL_LOCK_CH_XACT (2 << 12)