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| author | Shawn Guo <shawn.guo@linaro.org> | 2013-10-31 09:46:17 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-11-11 22:58:45 +0800 |
| commit | 43c9b9e8a4c64b1dd3026ab233703a4321ac6d7c (patch) | |
| tree | 214c780126ea7b8507dcb3f1e33d0dc824874386 /tools/perf/scripts/python/Perf-Trace-Util/Context.c | |
| parent | bc3b84da8a55752d8c54005e558d59ac10fe9953 (diff) | |
ARM: imx: set up pllv3 POWER and BYPASS sequentially
Currently, POWER and BYPASS bits are set up in a single write to pllv3
register. This causes problem occasionally from the IPU/HDMI testing.
Let's follow FSL BSP code to set up POWER bit, relock, and then BYPASS
sequentially.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/Context.c')
0 files changed, 0 insertions, 0 deletions