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authorKever Yang <kever.yang@rock-chips.com>2014-11-13 15:19:21 +0800
committerHeiko Stuebner <heiko@sntech.de>2014-11-16 00:02:24 +0100
commit0132234160ae46d8bd4677e37adb0b4366e05b1e (patch)
treebf44e88f39dfbda88915e3bf4a2530c8d009fb33 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py
parent9aa75e6e09620dbff3ae65ff3f03d2da3129b080 (diff)
clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register
According to rk3288 trm, the clk_usbphy480m_gate is located at bit 14 of CRU_CLKGATE5_CON register. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
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