diff options
| author | Gajanan Bhat <gajanan.bhat@intel.com> | 2012-03-28 13:39:30 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-03-28 23:55:36 +0200 |
| commit | 12a3c0551137425a9678d1b9f0495b625550f092 (patch) | |
| tree | 96f0dfa07499e8defc100db3dcc0782bc60a7f7b /tools/perf/scripts/python/check-perf-trace.py | |
| parent | fb046853ad66e64c96a2598f3fdd4cf5fbabc0d1 (diff) | |
drm/i915: program drain latency regs on ValleyView
This patch adds support for programming drain latency registers of Pondicherry
memory arbiter of Valleyview.
v2: clarify function names (Daniel)
fix summary typo (Daniel)
v3: add parens (Ben)
make drain function return bool (Ben)
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions