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| author | Akash Goel <akash.goel@intel.com> | 2014-04-04 17:14:38 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-04-09 14:37:09 +0200 |
| commit | 4e04632e882719e46edcbbc0b76fad778a0ed845 (patch) | |
| tree | 6ad57dc1883be6f750f3da27ffa7f1ef0ca6fa4b /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 8cbf3202098f191f8b0a0606b2df0af047f21fe5 (diff) | |
drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush'
On Gen4+ platforms (except BDW), Render Cache Operational flush
cannot be enabled.
This WA is apparently required for all Gen4+ platforms,except BDW.
In BDW, the bit has been repurposed otherwise.
This has been tested only on vlv.
v2: Corrected the code regarding the wrong usage of
MASKED_BIT_DISABLE (Chris)
v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville)
v4: Adding WA for g4x, crestline, broadwater (Ville)
Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions