diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-10-16 21:27:34 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-11-04 23:22:01 +0100 |
| commit | 61234fa5e5232c35f87d44d9d596af4b10eac255 (patch) | |
| tree | a63664a71dcba97d57a0604dadd381c21493b9a6 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 093e3f134e2eff13503f708b81aecc2501e7aecb (diff) | |
drm/i915: Wait for PHY port ready before link training on VLV/CHV
There's no point in checking if the data lanes came out of reset after
link training. If the data lanes aren't ready link training will fail
anyway.
Suggested-by: Todd Previte <tprevite@gmail.com>
Cc: Todd Previte <tprevite@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Acked-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions