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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-04-02 16:10:09 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-04-05 20:47:20 +0200 |
| commit | 9c8e09b7a551fc81842a2d9cdc3e42a5b729820f (patch) | |
| tree | bb3d1dd24b775960ab4dc554ce93e7f56e37d536 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 84b046f3985357a040721affebff8603264d793e (diff) | |
drm/i915: Set PIPECONF color range bit on Valleyview
VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: fixup rebase issues due to slightly different baseline.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions