diff options
| author | Brad Volkin <bradley.d.volkin@intel.com> | 2014-02-18 10:15:52 -0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-04-01 22:58:12 +0200 |
| commit | f0a346bdafaf6fc4a51df9ddf1548fd888f860d8 (patch) | |
| tree | d0d1fd5e54de83256b33a0ee1476fd76a1189f81 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 220375aa12c95744cd71d236f7c1ee39d277b6ed (diff) | |
drm/i915: Enable register whitelist checks
MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
commands allow userspace access to registers. Only certain registers
should be allowed for such access, so enable checking for those commands.
Each ring gets its own register whitelist.
MI_LOAD_REGISTER_REG on HSW also allows register access but is currently
unused by userspace components. Leave it rejected.
PIPE_CONTROL and MEDIA_VFE_STATE allow register access based on certain
bits being set. Reject those as well.
v2: trailing commas, rebased
OTC-Tracker: AXIA-4631
Change-Id: Ie614a2f0eb2e5917de809e5a17957175d24cc44f
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions