diff options
| author | Imre Deak <imre.deak@intel.com> | 2013-02-13 15:27:34 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-09-24 14:33:15 +0200 |
| commit | fbdcb06880bf414afafd4053d0d9906725f8b117 (patch) | |
| tree | fe29b594b9c49f0804426a5f9340dd34bd1f48dd /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 8a8b009d133714c0856ee08f7c68b908103e8383 (diff) | |
drm/i915/skl: don't set the AsyncFlip performance mode for Gen9+
The following sets the AsyncFlip performance mode for everything above
Gen6:
commit 4790cb36b3eede8fb0cca529dc1d31b9936fa24b
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sun Jan 20 16:11:20 2013 +0000
drm/i915: Disable AsyncFlip performance optimisations
Starting from Gen9 the MI_MODE register layout changes and doesn't
include the above bit.
Reviewed-by: Thomas Wood <thomas.wood@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions