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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-05-27 16:32:55 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-06-11 16:57:30 +0200
commit61407f6dd3c75ab900d52da4c29f9a52ed6b2acc (patch)
tree6c537aa7ead18fbc62f349f6e842889cbeee4ebf /tools/perf/scripts/python/event_analyzing_sample.py
parentb9e5ac3c181e4709e3e3bf3e280900186f5e0412 (diff)
drm/i915/chv: Force PHY clock buffers off after PLL disable
Now that we forced the clock buffers on in .pre_pll_enable() we should probably undo the damage after we've turned the PLL off. We do the clock buffer force enable in the .pre_pll_enable() hook as we need to know which port is going to be used, but in the disable case we don't need the port since we just disable the clock buffers to both channels. So we can do this in chv_disable_pll() instead of having to add any kind of .post_pll_disable() hook. v2: Improve the commit message Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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