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| author | Damien Lespiau <damien.lespiau@intel.com> | 2014-10-01 20:04:16 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-10-24 16:33:57 +0200 |
| commit | 95626e7caac4f0dbe285c59d9702b9f55af497eb (patch) | |
| tree | a4ad6f7b5f8bed567a1f781a16dcadc2b8294a66 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | cf404ce4b1de77017208e73c91cd6f09524678b7 (diff) | |
drm/i915: Use IS_HSW_ULT() in HSW CDCLK clock read-out
hsw_get_cdclk_freq() is really just HSW, so we can use IS_HSW_ULT()
instead of IS_ULT() there.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions