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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-10-04 20:32:25 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-10-10 12:46:57 +0200
commite1553faa904f3f8bdd734ee1404ce39c652bc9c6 (patch)
tree17267c8c11966a72b59f1af46b47c30992b93c4c /tools/perf/scripts/python/event_analyzing_sample.py
parentf01b796283e0fb2aa70b7cceb7067340f8ec6626 (diff)
drm/i915: Fix VGA_DISP_DISABLE check
The VGACNTRL register contains a bunch of other stuff besides the VGA_DISP_DISABLE bit. When we write the register we always set those other bits to zero, so normally the current check would work. However on HSW disabling and re-enabling the power well will reset the VGACNTRL register to its default value, which has several of the other bits set as well. So only look at the VGA_DISP_DISABLE bit when checking whether the VGA plane needs re-disabling. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
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