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| author | Ralf Baechle <ralf@linux-mips.org> | 2013-03-12 16:06:07 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-03-12 18:58:09 +0100 |
| commit | f4cdb6a00c148e7724ada0998643b293a52b5f62 (patch) | |
| tree | 69d7d9ccfca7d8f9fee2effd69a0b2ae055b3b2f /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 631b0af98c1efb160f02154743ae9f13fe03e347 (diff) | |
MIPS: SEAD3: Enable LL/SC.
All synthesizable CPU cores that could be loaded into a SEAD3's FPGA are
MIPS32 or MIPS64 CPUs that have ll/sc.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions