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| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2014-06-02 10:09:06 +0100 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2014-07-09 11:25:54 +0200 |
| commit | ff783233cc13eca99a3b59c0609c1ffc6164b7a2 (patch) | |
| tree | f1d5a88648b8e03b637e534871c7559b6416ff2d /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 6adb2a804a943a348eadfb09266571cd4557387c (diff) | |
mmc: mmci: Add Qcom datactrl register variant
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit position datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions