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| author | Eugeni Dodonov <eugeni.dodonov@intel.com> | 2012-03-29 12:32:24 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-09 18:04:00 +0200 |
| commit | 0e87f6679807a60efd3280c99544b6997916e987 (patch) | |
| tree | 6a20318673becda670282475ee83fa803a447115 /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | e7e104c3785a5a88ce9a58f0bfd0722e53217f47 (diff) | |
drm/i915: add DP_TP_CTL registers
This is one set of those registers for each pipe.
v2: use port enum to access individual registers
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions