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authorImre Deak <imre.deak@intel.com>2014-02-10 18:42:48 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-02-12 18:52:58 +0100
commit10c59c511101bb0726967c9f3a297c83f1b4203d (patch)
treeb1b5efe0c220cb86c1124c896217883b714354dc /tools/perf/scripts/python/failed-syscalls-by-pid.py
parent755e901964a979ea0e1a823ac8c5d477fe8fd108 (diff)
drm/i915: vlv: fix mapping of pipestat enable to status bits
At least on VLV we can't get at the pipestat status bits by simply right shifting the corresponding enable bits. The mapping between enable and status bits for the sprite0,1 flip done and the PSR events don't follow this rule, so we need to map them separately. The PSR enable for pipe A is DPFLIPSTAT[22], but I haven't added support for this, since there is no user of it atm. Until support is added WARN if someone tries to enable PSR interrupts, or tries to enable the same (1 << 6) bit on pipe B, which MBZ. v2: - inline the status->enable mask mapping (Ville) - fix bogus use of status bits in enable mask (Ville) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
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