summaryrefslogtreecommitdiffstats
path: root/tools/perf/scripts/python/failed-syscalls-by-pid.py
diff options
context:
space:
mode:
authorEugeni Dodonov <eugeni.dodonov@intel.com>2012-05-09 15:37:18 -0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-05-19 22:39:47 +0200
commitbf507ef7aaeed60b20aca9cf4b5a89060158724b (patch)
treec4764f90f0c55231338d4f0b9c7b5fa5e82aca3d /tools/perf/scripts/python/failed-syscalls-by-pid.py
parent9d82aa17407a9f3fcdd235799fa0eaed3ed1e2f1 (diff)
drm/i915: handle DDI-related assertions
Prevent bogus asserts on DDI-related paths. Longer explanation from Eugeni by mail: "For the asserts there are 3 paths where we hit them: - in assert_fdi_tx (we don't have the FDI_TX_CTL anymore, backup plan DDI_FUNC_CTL is used instead) - in assert_fdi_tx_pll_enabled (we have the combination of iCLKIP and DDI_FUNC_CTL, plus PORT_CLK_SEL and PIPE_CLK_SEL now to make things work). We could use an assert here indeed - if we configure port to use one clock, and pipe to use another, everything hangs. Right now, we configure all of them in one place only; but yes, when DP code lands it will get more funky. - and in ironlake_fdi_pll_enable. I reuse part of this function (to configure the TU sizes), but as in the 1st case, FDI_TX_CTL is gone so I just ignore it here." Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> [danvet: Pasted Eugeni's explanation into the commit message.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions