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authorShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>2013-12-14 16:23:53 +0100
committerSimon Horman <horms+renesas@verge.net.au>2014-02-04 10:22:52 +0900
commitcb9ec3adf882688831cdc9e7b84bb388f215f8ce (patch)
tree42187c0f9a3eda62b060ffae728e17ac8cfd4658 /tools/perf/scripts/python/futex-contention.py
parent017410f686b8d9928ce30e4eb146175ea672f4c9 (diff)
ARM: shmobile: r8a7790: Wait for status on all MSTP clocks
When enabling a module clock by clearing its bit in the MSTP control register, the CPG requires waiting for the status register to signal that the clock has started. Failure to do so will result in returning from the clk_enable() call with the clock potentially still disabled, leading to various race conditions and difficult to debug errors. Enable status wait for all MSTP clocks on the r8a7790. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
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