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author | Shobhit Kumar <shobhit.kumar@intel.com> | 2014-07-30 20:32:37 +0530 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-08-07 11:07:17 +0200 |
commit | f573de5a8474ae2cfc28424423c5a68c780a904b (patch) | |
tree | 98e80e5cb9a6b3802e5dc8caab768bdff40e1de9 /tools/perf/scripts/python/futex-contention.py | |
parent | aba86890a1785d787bfe7a741f910a472280540a (diff) |
drm/i915: Add correct hw/sw config check for DSI encoder
Check in vlv_crtc_clock_get if DPLL is enabled before calling dpio read.
It will not be enabled for DSI and avoid dpio read WARN dumps.
Absence of ->get_config was causing other WARN dumps as well. Update
dpll_hw_state as well correctly
v2: Address review comments by Daniel
- Check if DPLL is enabled rather than checking pipe output type
- set adjusted_mode->flags to 0 in compute_config rather than using
pipe_config->quirks
- Add helper function in intel_dsi_pll.c and use that in intel_dsi.c
- updated dpll_hw_state correctly
- Updated commit message and title
v3: Address review comments by Imre
- Proper masking of P1, M1 fields while computing divisors
- assert in case of bpp mismatch
- guard for divide by 0 while computing pclk
- Use ARRAY_SIZE instead of direct calculation
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions