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| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-12-02 09:46:19 +0000 |
|---|---|---|
| committer | Markos Chandras <markos.chandras@imgtec.com> | 2015-02-17 15:37:36 +0000 |
| commit | 5aed9da128be27275b0892fb413f3a0af64e00a6 (patch) | |
| tree | 26e82f80645bce9b6eec9db18d219c736fbc925a /tools/perf/scripts/python/net_dropmonitor.py | |
| parent | 28d6f93d201d20ce47a9e8414655569a78f0353c (diff) | |
MIPS: Add LLB bit and related feature for the Config 5 CP0 register
The LLBIT (bit 4) in the Config5 CP0 register indicates the software
availability of the Load-Linked bit. This bit is only set by hardware
and it has the following meaning:
0: LLB functionality is not supported
1: LLB functionality is supported. The following feature are also
supported:
- ERETNC instruction. Similar to ERET but it does not clear the LLB
bit in the LLAddr register.
- CP0 LLAddr/LLB bit must be set
- LLbit is software accessible through the LLAddr[0]
This will be used later on to emulate R2 LL/SC instructions.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'tools/perf/scripts/python/net_dropmonitor.py')
0 files changed, 0 insertions, 0 deletions