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authorMark Brown <broonie@opensource.wolfsonmicro.com>2013-03-29 20:50:07 +0000
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-03-30 13:52:36 +0000
commit75a5f89f635c2b7cd1f94fcaef5f764d480c8481 (patch)
treeb1ce46c87c4dfbcf03ac3109e061113eba7a0f12 /tools/perf/scripts/python/net_dropmonitor.py
parentcfdeb8c37ed32024dcb7d2e3bd70e2a9f9dfc0e6 (diff)
regmap: cache: Write consecutive registers in a single block write
When syncing blocks of data using raw writes combine the writes into a single block write, saving us bus overhead for setup, addressing and teardown. Currently the block write is done unconditionally as it is expected that hardware which has a register format which can support raw writes will support auto incrementing writes, this decision may need to be revised in future. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Reviewed-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
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