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| author | Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> | 2014-11-19 09:29:42 +0000 |
|---|---|---|
| committer | Markos Chandras <markos.chandras@imgtec.com> | 2015-02-16 14:02:50 +0000 |
| commit | a168b8f1cde6588ff7a67699fa11e01bc77a5ddd (patch) | |
| tree | c7c8e42b220c8a2af11c7aa99d14ad5e8fd8954b /tools/perf/scripts/python/net_dropmonitor.py | |
| parent | 51eec48e1252ea39d21b5206e4962f09f823a369 (diff) | |
MIPS: mm: Add MIPS R6 instruction encodings
MIPS R6 defines new opcodes for ll, sc, cache and pref instructions
so we need to take these into consideration in the micro-assembler.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'tools/perf/scripts/python/net_dropmonitor.py')
0 files changed, 0 insertions, 0 deletions