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authorDaniel Vetter <daniel.vetter@ffwll.ch>2014-04-24 23:55:11 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-05-20 14:10:00 +0200
commitbdd4b6a655749970cc632aafc5fd596c07b60b1c (patch)
treecffa7ea1e9390d4e49754fdbd37eae0078d1106f /tools/perf/scripts/python/sched-migration.py
parentf13c2ef368d94b7f0bb7b89ad45a9370e3044ce0 (diff)
drm/i915: Extract vlv_prepare_pll
With this all hw writes are also gone from the ->crtc_mode_set hook on vlv. I wondered whether we should track more of the pll state in the pipe config, but otoh as long as we don't have shared plls that's not really useful - the cross-checking of the port clock should be sufficient. While at it also de-magic some of the pipe checks, this has been irking me since a long time. Whit this vlv is now ready for runtime PM on dpms. If we'd have runtime PM support in general ... Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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