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authorAlexander Duyck <alexander.h.duyck@intel.com>2012-02-08 07:51:16 +0000
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2012-03-19 01:54:36 -0700
commitd3ee42944393895374e2f321f54e9a701e9f965c (patch)
treea281e0308cd66eddce36d7958f935059ca1358d6 /tools/perf/scripts/python/sched-migration.py
parent244e27ad4d9e561c688c4da3383fec890be832d0 (diff)
ixgbe: Update layout of ixgbe_ring structure to improve cache performance
This change makes it so that only the 2nd cache line in the ring structure should see frequent updates. The advantage to this is that it should reduce the amount of cross CPU cache bouncing since only the 2nd cache line will be changing between most network transactions. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Stephen Ko <stephen.s.ko@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
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