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| author | Rodrigo Vivi <rodrigo.vivi@gmail.com> | 2013-05-09 14:20:50 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-10 21:56:50 +0200 |
| commit | d89f2071461d5682b897c73278daaf25fd11aff5 (patch) | |
| tree | 7c82a423f5dd3d52a4b88ef6a426eccfb351f092 /tools/perf/scripts/python/sched-migration.py | |
| parent | 285541647a816e00348916ba7387eeacea30eba9 (diff) | |
drm/i915: HSW FBC WaFbcDisableDpfcClockGating
Display register 46500h bit 23 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
v2: Ville suggested to enable it back when disabling fbc to avoid wasting
power.
v3: RMW to preserve other bits (by Ville)
v4: Fix from Ville: sed &/| at RMW
v5: Too far on sed.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Insert missing space that checkpatch spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions