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| author | Nicolas Pitre <nicolas.pitre@linaro.org> | 2013-07-16 20:59:53 -0400 |
|---|---|---|
| committer | Nicolas Pitre <nicolas.pitre@linaro.org> | 2013-07-22 12:26:09 -0400 |
| commit | e8f9bb1bd6bb93fff773345cc54c42585e0e3ece (patch) | |
| tree | 730257640b01d6b83b3a37d0c4961e0189faaddc /tools/perf/scripts/python/sched-migration.py | |
| parent | 3b2f64d00c46e1e4e9bd0bb9bb12619adac27a4b (diff) | |
ARM: vexpress/dcscb: fix cache disabling sequences
Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the
cache when the CTRL.C bit is cleared. Let's ensure there is no memory
access within the disable and flush cache sequence, including to the
stack.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions