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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-01-25 21:44:41 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-01-26 17:29:45 +0100 |
| commit | fc2de40986f5a35c02f06dea4221113b3a7a7c3c (patch) | |
| tree | 5dda4cb528b994e35bca8674c4e28848cf69bfe2 /tools/perf/scripts/python/sched-migration.py | |
| parent | fba5d532d16db812dabaa80fb7570820daa2707b (diff) | |
drm/i915: PLL registers need an offset on VLV
v2: Dropped the clock gating registers
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions