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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-01-24 15:29:46 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-01-24 23:13:13 +0100 |
| commit | 4e8e7eb70388c90a2d0ea2ccf951b11c3ec24b3e (patch) | |
| tree | e30e456d03ce4b8ad85e3ed4980b425efd7d3e62 /tools/perf/scripts/python/sctop.py | |
| parent | 67d62c57465e5da7647cb13ef567b80f6deb9a3c (diff) | |
drm/i915: Pipe timing registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/sctop.py')
0 files changed, 0 insertions, 0 deletions