diff options
| author | Roger Quadros <rogerq@ti.com> | 2014-05-05 12:54:43 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-05-14 14:39:34 -0700 |
| commit | 032d774575dfed145e4477b47579fd51d9c102b3 (patch) | |
| tree | 09cf7b8a4a762d950b3c3e2c4025c999238d8818 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | c65d0ad51022b2fa250a3561cc370fcbfe23beda (diff) | |
ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate
This clock gate description is missing in the older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.
Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900,
Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL
Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
usb_otg_ss2_refclk960m.
CC: Benoît Cousson <bcousson@baylibre.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions