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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-07-04 11:02:03 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-07-16 07:57:42 +0200 |
| commit | 0d8ff15e9a15f2b393e53337a107b7a1e5919b6d (patch) | |
| tree | 641bb75068c873958a52cb38b9cb8ed9bacffd0b /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 50b44a449ff1a19712ebc36ffccf9ac0a68033bf (diff) | |
drm/i915/hsw: Set correct Haswell PTE encodings.
The cacheability controls have changed, and the bits have been
rearranged in general.
Note that age 0 is the oldest (most likely to get evicted) and age 3
is the youngest (most likely to stick around for a bit). We've picked
0 for no reason, but atm it shouldn't matter anyway (since we don't
yet try to differentiate between different objects).
v2: Remove comments for snb/ivb cache leves, that's a separate change.
v3: Resolve conflicts due to patch series reordering.
v4: Rebased on top of Kenneth Graunke's ->pte_encode refactoring.
v5: Removed eLLC bits for separate patch.
In the internal repository this was:
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Add comment about cache ages as requested by Ben provoked due
to a question from Damien.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions