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authorMurali Karicheri <m-karicheri2@ti.com>2013-11-23 16:26:52 -0500
committerSantosh Shilimkar <santosh.shilimkar@ti.com>2013-12-10 11:08:20 -0500
commitdbb4e67fe7088f963007453ee07e453c4e1fab28 (patch)
treea5e0fc1fbb0ad4f659f2acc47b00d35cbe7a5506 /tools/perf/scripts/python/syscall-counts-by-pid.py
parent6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae (diff)
clk: keystone: use clkod register bits for postdiv
DDR3A/B, ARM and PA PLL controllers have clkod register bits for configuring postdiv values. So use it instead of using fixed post dividers for these pll controllers. Assume that if fixed-postdiv attribute is not present, use clkod register value for pistdiv. Also update the Documentation of bindings to reflect the same. Cc: Mike Turquette <mturquette@linaro.org Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
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