diff options
| author | Minghuan Lian <Minghuan.Lian@freescale.com> | 2013-06-21 18:59:12 +0800 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2013-08-07 18:38:05 -0500 |
| commit | 03daa99ef50873651e363fc12ae0b5facdb3f831 (patch) | |
| tree | 4c8222c81d769dfbd1186f47aaf06a8b95e33835 /tools/perf/scripts/python/syscall-counts.py | |
| parent | df1024ad87286c5935d4ebb5153bf4cebf45eb8a (diff) | |
powerpc/dts: update MSI bindings doc for MPIC v4.3
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. When using
MSIR1, the interrupt number is not consecutive. It is hard to use
'msi-available-ranges' to describe the ranges of the available
interrupt, so MPIC v4.3 does not support this property.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
[scottwood@freescale.com: minor grammar fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions