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| author | Fabio Estevam <fabio.estevam@freescale.com> | 2014-08-19 15:21:12 -0300 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-09-16 10:06:46 +0800 |
| commit | 0783a56087e9ecfae2f01f9662ff52081c5b5e25 (patch) | |
| tree | da9719b2d2478b123e13aa1cf6ac0bd5b2d7cdaf /tools/perf/scripts/python/syscall-counts.py | |
| parent | bad66c3ebdcdb4043bdcfe24ddab4802d5fc4327 (diff) | |
ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks
PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and
PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions