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| author | Hariprasad Shenai <hariprasad@chelsio.com> | 2014-09-01 19:54:57 +0530 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-09-01 23:00:41 -0700 |
| commit | 9bb59b96ae88ee9dc035d5cc9818b02b12208904 (patch) | |
| tree | 4e6795065995b7e9e126c0133c8e09d35b5a7eca /tools/perf/scripts/python/syscall-counts.py | |
| parent | 63a92fe6f7e40069086be21bf9fbcfbe8d001345 (diff) | |
cxgb4: Fix T5 adapter accessing T4 adapter registers
Fixes few register access for both T4 and T5.
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS & PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS
is T4 only register don't let T5 access them. For T5 MA_PARITY_ERROR_STATUS2
is additionally read. MPS_TRC_RSS_CONTROL is T4 only register, for T5 use
MPS_T5_TRC_RSS_CONTROL.
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions