diff options
| author | Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> | 2011-07-14 09:52:38 +0900 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2011-07-25 19:11:12 +0530 |
| commit | 0b052f4a088ddc47a5da23dd733522241314cfb4 (patch) | |
| tree | 8367cd4cb3dd7fd7e5c01c2b6117755c6e9ea72e /tools/perf/scripts/python | |
| parent | 95bfea1675c02d83cf1923272e62f91db11cbb8f (diff) | |
pch_dma: Fix CTL register access issue
Currently, Mode-Control register is accessed by read-modify-write.
According to DMA hardware specifications datasheet, prohibits this method.
Because this register resets to 0 by DMA HW after DMA transfer completes.
Thus, current read-modify-write processing can cause unexpected behavior.
The datasheet says in case of writing Mode-Control register, set the value for only target channel, the others must set '11b'.
e.g. Set DMA0=01b DMA11=10b
CTL0=33333331h
CTL2=00002333h
NOTE:
CTL0 includes DMA0~7 Mode-Control register.
CTL2 includes DMA8~11 Mode-Control register.
This patch modifies the issue.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions