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| author | Casey Leedom <leedom@chelsio.com> | 2013-08-06 15:48:37 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2013-08-12 13:58:14 -0600 |
| commit | 2c6217e0fc5f6c7458f413346806061d97ce37cf (patch) | |
| tree | 1a7a54f2758feeba2a0466e76e0c636420b1310c /tools/perf/scripts/python | |
| parent | 3775a209d38aa3a0c7ed89a7d0f529e0230f280e (diff) | |
PCI: Chelsio quirk: Enable Bus Master during Function-Level Reset
T4 can wedge if there are DMAs in flight within the chip and Bus
Master has been disabled. We need to have it on till the Function
Level Reset completes. T4 can also suffer a Head Of Line blocking
problem if MSI-X interrupts are disabled before the FLR has completed.
Signed-off-by: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions