diff options
| author | Chon Ming Lee <chon.ming.lee@intel.com> | 2013-09-25 15:47:51 +0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-01 07:45:22 +0200 |
| commit | 58f6e632d5d24f1f510bafccc4c963a06f6a55a8 (patch) | |
| tree | ad65a36cbff69bd5c7e2760f6998f98d08c4d9ca /tools/perf/scripts/python | |
| parent | 814e9b57c0cb56ef1f56c3099f130a3e5373564e (diff) | |
drm/i915: Fix VLV eDP timing v2
Fix the typo in previous commit for DP 1.62 divisor.
drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
v2: sigh, the m1 div is 3.
Reported-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions