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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-09-19 17:03:06 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-10 12:47:11 +0200 |
| commit | 5ade2c2f5813733f23bbb2f21e8ba5c3f8474a2b (patch) | |
| tree | 634cd7d8f67829cde94970318d270501c4684eab /tools/perf/scripts/python | |
| parent | 076e29f225bb7a5d97fa95b78b8dca61599b4198 (diff) | |
drm/i915: wait for IPS_ENABLE when enabling IPS
At the end of haswell_crtc_enable we have an intel_wait_for_vblank
with a big comment, and the message suggests it's a workaround for
something we don't really understand. So I removed that wait and
started getting HW state readout error messages saying that the IPS
state is not what we expected.
I investigated and concluded that after you write IPS_ENABLE to
IPS_CTL, the bit will only actually become 1 on the next vblank. So
add code to wait for the IPS_ENABLE bit. We don't really need this
wait right now due to the wait I already mentioned, but at least this
one has a reason to be there, while the other one is just to
workaround some problem: we may remove it in the future.
The wait also acts as a POSTING_READ which we missed.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions