diff options
| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2013-03-27 23:07:05 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2013-03-28 14:41:18 -0400 |
| commit | 749a2b66f49de322ae472d57e1451e5f623d82f1 (patch) | |
| tree | 0c648bb9699acd282f6048841dfdb7e17651c240 /tools/perf/scripts/python | |
| parent | 19e016d6be4178dd1b20ab95254089538e71adab (diff) | |
net/macb: clear tx/rx completion flags in ISR
At least in the cadence IP core on the Xilinx Zynq SoC the TCOMP/RCOMP flags
are not auto-cleaned. As these flags are evaluated, they need to be cleaned.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions