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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-01-28 23:48:46 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-02-10 17:43:49 +0100
commit75c13993db592343bda1fd62f2555fea037d56bd (patch)
treee21d84f7ac42b4173a3b5be45b20355cab995b23 /tools/perf/scripts/python
parentc3febcc438ba0878b164c74310bd77c50dbb0ba8 (diff)
drm/i915: fixup overlay checks for interlaced modes
The drm core _really_ likes to frob around with the crtc timings and put halfed vertical timings (in fields) in there. Which confuses the overlay code, resulting in it's refusal to display anything at the lower half of an interlaced pipe. Tested-by: Christopher Egert <cme3000@gmail.com> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
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