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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2014-05-12 16:22:12 +0200
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-05-12 16:48:51 +0200
commitb1059186299df841a8774b5cd76bdd06dbc566f3 (patch)
tree3ba9d7375188a9f3f3280cc252131712668d08ac /tools/perf/scripts/python
parent27a96a0364787d2b41d2a72d08143d95263e1b07 (diff)
ARM: at91/dt: sam9261: Fix PLL output ranges and other clocks divisors
Argument 3 (OUT) and 4 (ICPLL) of the atmel,pll-clk-output-ranges were missing. Also, the at91sam9261 doesn't really have a by 3 divisor. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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